[llvm] 2aac00e - [RISCV] Add more tests for vcpop and vfirst with VL=0
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 23 21:59:37 PST 2022
Author: Chenbing.Zheng
Date: 2022-02-24T05:59:12Z
New Revision: 2aac00e4a685525bd7c09bc71522f5a56adf4613
URL: https://github.com/llvm/llvm-project/commit/2aac00e4a685525bd7c09bc71522f5a56adf4613
DIFF: https://github.com/llvm/llvm-project/commit/2aac00e4a685525bd7c09bc71522f5a56adf4613.diff
LOG: [RISCV] Add more tests for vcpop and vfirst with VL=0
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D120300
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/vcpop.ll
llvm/test/CodeGen/RISCV/rvv/vfirst.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/vcpop.ll b/llvm/test/CodeGen/RISCV/rvv/vcpop.ll
index 1b77ec8dd82e0..2006481ba4692 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vcpop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vcpop.ll
@@ -21,6 +21,20 @@ entry:
ret iXLen %a
}
+define iXLen @intrinsic_vcpop_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind {
+; CHECK-LABEL: intrinsic_vcpop_m_nxv1i1_zero:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetivli zero, 0, e8, mf8, ta, mu
+; CHECK-NEXT: vcpop.m a0, v0
+; CHECK-NEXT: ret
+entry:
+ %a = call iXLen @llvm.riscv.vcpop.iXLen.nxv1i1(
+ <vscale x 1 x i1> %0,
+ iXLen 0)
+
+ ret iXLen %a
+}
+
declare iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
@@ -43,6 +57,23 @@ entry:
ret iXLen %a
}
+define iXLen @intrinsic_vcpop_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
+; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv1i1_zero:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetivli zero, 0, e8, mf8, ta, mu
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vcpop.m a0, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
+ <vscale x 1 x i1> %0,
+ <vscale x 1 x i1> %1,
+ iXLen 0)
+
+ ret iXLen %a
+}
+
declare iXLen @llvm.riscv.vcpop.iXLen.nxv2i1(
<vscale x 2 x i1>,
iXLen);
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfirst.ll b/llvm/test/CodeGen/RISCV/rvv/vfirst.ll
index 5d71c17db6c29..f42abf7fee650 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfirst.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfirst.ll
@@ -21,6 +21,20 @@ entry:
ret iXLen %a
}
+define iXLen @intrinsic_vfirst_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind {
+; CHECK-LABEL: intrinsic_vfirst_m_nxv1i1_zero:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetivli zero, 0, e8, mf8, ta, mu
+; CHECK-NEXT: vfirst.m a0, v0
+; CHECK-NEXT: ret
+entry:
+ %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1(
+ <vscale x 1 x i1> %0,
+ iXLen 0)
+
+ ret iXLen %a
+}
+
declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
@@ -43,6 +57,23 @@ entry:
ret iXLen %a
}
+define iXLen @intrinsic_vfirst_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
+; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv1i1_zero:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vsetivli zero, 0, e8, mf8, ta, mu
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vfirst.m a0, v9, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
+ <vscale x 1 x i1> %0,
+ <vscale x 1 x i1> %1,
+ iXLen 0)
+
+ ret iXLen %a
+}
+
declare iXLen @llvm.riscv.vfirst.iXLen.nxv2i1(
<vscale x 2 x i1>,
iXLen);
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