[llvm] c7d6448 - [DAGCombiner][TargetLowering] Pass SDValue by value to isMulAddWithConstProfitable.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 23 12:41:29 PST 2022
Author: Craig Topper
Date: 2022-02-23T12:40:45-08:00
New Revision: c7d6448d037e2c053bcb19a8398653f1d31ca3de
URL: https://github.com/llvm/llvm-project/commit/c7d6448d037e2c053bcb19a8398653f1d31ca3de
DIFF: https://github.com/llvm/llvm-project/commit/c7d6448d037e2c053bcb19a8398653f1d31ca3de.diff
LOG: [DAGCombiner][TargetLowering] Pass SDValue by value to isMulAddWithConstProfitable.
Internally to DAGCombiner the SDValues were passed by non-const
reference despite not being modified. They were then passed by
const reference to TLI.
This patch passes them by value which is consistent with the vast
majority of code.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D120420
Added:
Modified:
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 2e17722180dd4..fbb9767e4da71 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -2128,8 +2128,8 @@ class TargetLoweringBase {
/// about some cases, a default true can be returned to let the DAGCombiner
/// decide.
/// AddNode is (add x, c1), and ConstNode is c2.
- virtual bool isMulAddWithConstProfitable(const SDValue &AddNode,
- const SDValue &ConstNode) const {
+ virtual bool isMulAddWithConstProfitable(SDValue AddNode,
+ SDValue ConstNode) const {
return true;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4ed38c3ea243c..3544729da2f71 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -666,9 +666,8 @@ namespace {
/// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
/// MulNode is the original multiply, AddNode is (add x, c1),
/// and ConstNode is c2.
- bool isMulAddWithConstProfitable(SDNode *MulNode,
- SDValue &AddNode,
- SDValue &ConstNode);
+ bool isMulAddWithConstProfitable(SDNode *MulNode, SDValue AddNode,
+ SDValue ConstNode);
/// This is a helper function for visitAND and visitZERO_EXTEND. Returns
/// true if the (and (load x) c) pattern matches an extload. ExtVT returns
@@ -17355,9 +17354,8 @@ SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
// (A + c1) * c3
// (A + c2) * c3
// We're checking for cases where we have common "c3 * A" expressions.
-bool DAGCombiner::isMulAddWithConstProfitable(SDNode *MulNode,
- SDValue &AddNode,
- SDValue &ConstNode) {
+bool DAGCombiner::isMulAddWithConstProfitable(SDNode *MulNode, SDValue AddNode,
+ SDValue ConstNode) {
APInt Val;
// If the add only has one use, and the target thinks the folding is
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 2fe77449b3a07..cc0e8b37c184b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -12905,7 +12905,7 @@ bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
// (mul (add x, c1), c2) -> (add (mul x, c2), c2*c1) in DAGCombine,
// if the folding leads to worse code.
bool AArch64TargetLowering::isMulAddWithConstProfitable(
- const SDValue &AddNode, const SDValue &ConstNode) const {
+ SDValue AddNode, SDValue ConstNode) const {
// Let the DAGCombiner decide for vector types and large types.
const EVT VT = AddNode.getValueType();
if (VT.isVector() || VT.getScalarSizeInBits() > 64)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 9bd33bf0bcf2e..0d2df1002bb12 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -601,8 +601,8 @@ class AArch64TargetLowering : public TargetLowering {
bool isLegalAddImmediate(int64_t) const override;
bool isLegalICmpImmediate(int64_t) const override;
- bool isMulAddWithConstProfitable(const SDValue &AddNode,
- const SDValue &ConstNode) const override;
+ bool isMulAddWithConstProfitable(SDValue AddNode,
+ SDValue ConstNode) const override;
bool shouldConsiderGEPOffsetSplit() const override;
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cdf5caff228e5..f0fc308410125 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -19406,8 +19406,8 @@ bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
// Return false to prevent folding
// (mul (add r, c0), c1) -> (add (mul r, c1), c0*c1) in DAGCombine,
// if the folding leads to worse code.
-bool ARMTargetLowering::isMulAddWithConstProfitable(
- const SDValue &AddNode, const SDValue &ConstNode) const {
+bool ARMTargetLowering::isMulAddWithConstProfitable(SDValue AddNode,
+ SDValue ConstNode) const {
// Let the DAGCombiner decide for vector types and large types.
const EVT VT = AddNode.getValueType();
if (VT.isVector() || VT.getScalarSizeInBits() > 32)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 08ccd9db1bb01..df1dc2a9a7ae3 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -713,8 +713,8 @@ class VectorType;
Align Alignment,
const DataLayout &DL) const;
- bool isMulAddWithConstProfitable(const SDValue &AddNode,
- const SDValue &ConstNode) const override;
+ bool isMulAddWithConstProfitable(SDValue AddNode,
+ SDValue ConstNode) const override;
bool alignLoopsWithOptSize() const override;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index fbe767a4897d9..b8969a327d078 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11262,8 +11262,8 @@ bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
return false;
}
-bool RISCVTargetLowering::isMulAddWithConstProfitable(
- const SDValue &AddNode, const SDValue &ConstNode) const {
+bool RISCVTargetLowering::isMulAddWithConstProfitable(SDValue AddNode,
+ SDValue ConstNode) const {
// Let the DAGCombiner decide for vectors.
EVT VT = AddNode.getValueType();
if (VT.isVector())
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 2a4fa57aad662..6118d9be9ffff 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -497,8 +497,8 @@ class RISCVTargetLowering : public TargetLowering {
bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
SDValue C) const override;
- bool isMulAddWithConstProfitable(const SDValue &AddNode,
- const SDValue &ConstNode) const override;
+ bool isMulAddWithConstProfitable(SDValue AddNode,
+ SDValue ConstNode) const override;
TargetLowering::AtomicExpansionKind
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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