[PATCH] D117507: [PowerPC] Add the Power10 LXVKQ instrution.

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp updated this revision to Diff 410797.
stefanp added a comment.

Rebased the patch.
Moved the def for LXVKQ lower down.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117507/new/

https://reviews.llvm.org/D117507

Files:
  llvm/lib/Target/PowerPC/P10InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstrP10.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
  llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s


Index: llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
===================================================================
--- llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -528,6 +528,9 @@
 # CHECK-LE: xxeval 32, 1, 2, 3, 2                 # encoding: [0x02,0x00,0x00,0x05,
 # CHECK-LE-SAME:                                               0xd1,0x10,0x01,0x88]
             xxeval 32, 1, 2, 3, 2
+# CHECK-BE: lxvkq 63, 31                          # encoding: [0xf3,0xff,0xfa,0xd1]
+# CHECK-LE: lxvkq 63, 31                          # encoding: [0xd1,0xfa,0xff,0xf3]
+            lxvkq 63, 31
 # CHECK-BE: vclzdm 1, 2, 3                        # encoding: [0x10,0x22,0x1f,0x84]
 # CHECK-LE: vclzdm 1, 2, 3                        # encoding: [0x84,0x1f,0x22,0x10]
             vclzdm 1, 2, 3
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
===================================================================
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
@@ -364,6 +364,9 @@
 # CHECK: xxeval 32, 1, 2, 3, 2
 0x05 0x00 0x00 0x02 0x88 0x01 0x10 0xd1
 
+# CHECK: lxvkq 63, 31
+0xf3 0xff 0xfa 0xd1
+
 # CHECK: vclzdm 1, 2, 3
 0x10 0x22 0x1f 0x84
 
Index: llvm/lib/Target/PowerPC/PPCInstrP10.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -655,6 +655,22 @@
   let Inst{31} = 0;
 }
 
+// X-Form: [ PO T EO UIM XO TX ]
+class XForm_XT6_IMM5<bits<6> opcode, bits<5> eo, bits<10> xo, dag OOL, dag IOL,
+                     string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<5> UIM;
+
+  let Pattern = pattern;
+
+  let Inst{6-10} = XT{4-0};
+  let Inst{11-15} = eo;
+  let Inst{16-20} = UIM;
+  let Inst{21-30} = xo;
+  let Inst{31} = XT{5};
+}
+
 class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
                            string asmstr, InstrItinClass itin,
                            list<dag> pattern>
@@ -2393,6 +2409,8 @@
   def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
   def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;
   def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
+  def LXVKQ : XForm_XT6_IMM5<60, 31, 360, (outs vsrc:$XT), (ins u5imm:$UIM),
+                             "lxvkq $XT, $UIM", IIC_VecGeneral, []>;
 }
 
 let Predicates = [IsISA3_1, HasVSX] in {
Index: llvm/lib/Target/PowerPC/P10InstrResources.td
===================================================================
--- llvm/lib/Target/PowerPC/P10InstrResources.td
+++ llvm/lib/Target/PowerPC/P10InstrResources.td
@@ -1625,6 +1625,7 @@
       (instrs
     LVSL,
     LVSR,
+    LXVKQ,
     MFVSRLD,
     MTVSRWS,
     VCLZLSBB,


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