[llvm] 5658d86 - AArch64: clamp UBFX high-bit to 32-bits

[Tim Northover via llvm-commits]

Author: Tim Northover
Date: 2022-02-23T12:48:39Z
New Revision: 5658d869ff4cefc5c3626f7e5658bb43b2b32063

URL: https://github.com/llvm/llvm-project/commit/5658d869ff4cefc5c3626f7e5658bb43b2b32063
DIFF: https://github.com/llvm/llvm-project/commit/5658d869ff4cefc5c3626f7e5658bb43b2b32063.diff

LOG: AArch64: clamp UBFX high-bit to 32-bits

We were producing invalid instructions like "ubfx w0, w0, #20, #16".

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    llvm/test/CodeGen/AArch64/bitfield.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 770a5bbb0717f..c8a26247e228b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -1852,6 +1852,7 @@ static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
     VT = Opd0->getValueType(0);
   } else if (isOpcWithIntImmediate(Op0, ISD::SRL, SrlImm)) {
     Opd0 = Op0->getOperand(0);
+    ClampMSB = (VT == MVT::i32);
   } else if (BiggerPattern) {
     // Let's pretend a 0 shift right has been performed.
     // The resulting code will be at least as good as the original one

diff  --git a/llvm/test/CodeGen/AArch64/bitfield.ll b/llvm/test/CodeGen/AArch64/bitfield.ll
index 2ea0a41466144..58fd0db036caa 100644
--- a/llvm/test/CodeGen/AArch64/bitfield.ll
+++ b/llvm/test/CodeGen/AArch64/bitfield.ll
@@ -230,3 +230,16 @@ define dso_local i64 @test_sbfx64(i64* %addr) {
    %extended = ashr i64 %shifted, 1
    ret i64 %extended
 }
+
+define i32 @test_ubfx_mask(i32 %lhs, i32 %rhs) {
+; CHECK-LABEL: test_ubfx_mask:
+; CHECK: lsr w0, w1, #20
+  %mask = and i32 %lhs, 20
+  %i7 = add i32 %mask, 1
+  %i8 = xor i32 %lhs, 20
+  %i9 = xor i32 %i8, %i7
+  %i10 = and i32 %i9, 20
+  %shift = lshr i32 %rhs, %i10
+  %shift.masked = and i32 %shift, 65535
+  ret i32 %shift.masked
+}