[llvm] 7abcb7b - [RISCV] Supplement more tests for GREVI aliaes in Zbp extension
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 22 22:17:10 PST 2022
Author: Lian Wang
Date: 2022-02-23T06:15:52Z
New Revision: 7abcb7ba87b10544b8a7c52015a2951e509f765e
URL: https://github.com/llvm/llvm-project/commit/7abcb7ba87b10544b8a7c52015a2951e509f765e
DIFF: https://github.com/llvm/llvm-project/commit/7abcb7ba87b10544b8a7c52015a2951e509f765e.diff
LOG: [RISCV] Supplement more tests for GREVI aliaes in Zbp extension
Supplement tests for some aliaes of grevi.
RV32:
add rev4.h/rev2.h in rv32zbp.ll
add rev/rev2/rev4/rev8/rev16 in rv32zbp-intrinsic.ll
RV64:
add rev4.h/rev2.h in rv64zbp.ll
add rev.h/rev/rev2/rev4/rev8/rev16/rev32/rev.w/rev2.w/
rev4.w/rev8.w/rev16.w in rv64zbp-intrinsic.ll
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D120304
Added:
Modified:
llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
llvm/test/CodeGen/RISCV/rv32zbp.ll
llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zbp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
index 4f5ccca74b2cb..475d3b5460993 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
@@ -32,6 +32,51 @@ define i32 @grevi32(i32 %a) nounwind {
ret i32 %tmp
}
+define i32 @revi32(i32 %a) nounwind {
+; RV32ZBP-LABEL: revi32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev a0, a0
+; RV32ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 31)
+ ret i32 %tmp
+}
+
+define i32 @rev2i32(i32 %a) nounwind {
+; RV32ZBP-LABEL: rev2i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev2 a0, a0
+; RV32ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 30)
+ ret i32 %tmp
+}
+
+define i32 @rev4i32(i32 %a) nounwind {
+; RV32ZBP-LABEL: rev4i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev4 a0, a0
+; RV32ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 28)
+ ret i32 %tmp
+}
+
+define i32 @rev8i32(i32 %a) nounwind {
+; RV32ZBP-LABEL: rev8i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev8 a0, a0
+; RV32ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 24)
+ ret i32 %tmp
+}
+
+define i32 @rev16i32(i32 %a) nounwind {
+; RV32ZBP-LABEL: rev16i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev16 a0, a0
+; RV32ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.grev.i32(i32 %a, i32 16)
+ ret i32 %tmp
+}
+
declare i32 @llvm.riscv.gorc.i32(i32 %a, i32 %b)
define i32 @gorc32(i32 %a, i32 %b) nounwind {
diff --git a/llvm/test/CodeGen/RISCV/rv32zbp.ll b/llvm/test/CodeGen/RISCV/rv32zbp.ll
index 7e113d6be7d0a..7203aeb2a99b6 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbp.ll
@@ -1607,6 +1607,100 @@ define i32 @grev8_i32(i32 %a) nounwind {
ret i32 %or
}
+define i32 @grev12_i32(i32 %a) nounwind {
+; RV32I-LABEL: grev12_i32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a1, a0, 4
+; RV32I-NEXT: lui a2, 986895
+; RV32I-NEXT: addi a2, a2, 240
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: srli a0, a0, 4
+; RV32I-NEXT: lui a2, 61681
+; RV32I-NEXT: addi a2, a2, -241
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: slli a1, a0, 8
+; RV32I-NEXT: lui a2, 1044496
+; RV32I-NEXT: addi a2, a2, -256
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: srli a0, a0, 8
+; RV32I-NEXT: lui a2, 4080
+; RV32I-NEXT: addi a2, a2, 255
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32ZBP-LABEL: grev12_i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev4.h a0, a0
+; RV32ZBP-NEXT: ret
+ %and1 = shl i32 %a, 4
+ %shl1 = and i32 %and1, -252645136
+ %and1b = lshr i32 %a, 4
+ %shr1 = and i32 %and1b, 252645135
+ %or1 = or i32 %shl1, %shr1
+ %and2 = shl i32 %or1, 8
+ %shl2 = and i32 %and2, -16711936
+ %and2b = lshr i32 %or1, 8
+ %shr2 = and i32 %and2b, 16711935
+ %or2 = or i32 %shl2, %shr2
+ ret i32 %or2
+}
+
+define i32 @grev14_i32(i32 %a) nounwind {
+; RV32I-LABEL: grev14_i32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: slli a1, a0, 2
+; RV32I-NEXT: lui a2, 838861
+; RV32I-NEXT: addi a2, a2, -820
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: srli a0, a0, 2
+; RV32I-NEXT: lui a2, 209715
+; RV32I-NEXT: addi a2, a2, 819
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: slli a1, a0, 4
+; RV32I-NEXT: lui a2, 986895
+; RV32I-NEXT: addi a2, a2, 240
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: srli a0, a0, 4
+; RV32I-NEXT: lui a2, 61681
+; RV32I-NEXT: addi a2, a2, -241
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: slli a1, a0, 8
+; RV32I-NEXT: lui a2, 1044496
+; RV32I-NEXT: addi a2, a2, -256
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: srli a0, a0, 8
+; RV32I-NEXT: lui a2, 4080
+; RV32I-NEXT: addi a2, a2, 255
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32ZBP-LABEL: grev14_i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: rev2.h a0, a0
+; RV32ZBP-NEXT: ret
+ %and1 = shl i32 %a, 2
+ %shl1 = and i32 %and1, -858993460
+ %and1b = lshr i32 %a, 2
+ %shr1 = and i32 %and1b, 858993459
+ %or1 = or i32 %shl1, %shr1
+ %and2 = shl i32 %or1, 4
+ %shl2 = and i32 %and2, -252645136
+ %and2b = lshr i32 %or1, 4
+ %shr2 = and i32 %and2b, 252645135
+ %or2 = or i32 %shl2, %shr2
+ %and3 = shl i32 %or2, 8
+ %shl3 = and i32 %and3, -16711936
+ %and3b = lshr i32 %or2, 8
+ %shr3 = and i32 %and3b, 16711935
+ %or3 = or i32 %shl3, %shr3
+ ret i32 %or3
+}
+
define i64 @grev8_i64(i64 %a) nounwind {
; RV32I-LABEL: grev8_i64:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
index b236fb6f060e8..b82d520efbfa0 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
@@ -342,6 +342,114 @@ define i64 @grevi64(i64 %a) nounwind {
ret i64 %tmp
}
+define i64 @revhwi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: revhwi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev.h a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 15)
+ ret i64 %tmp
+}
+
+define i64 @rev16wi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: rev16wi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev16.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 16)
+ ret i64 %tmp
+}
+
+define i64 @rev8wi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: rev8wi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev8.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 24)
+ ret i64 %tmp
+}
+
+define i64 @rev4wi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: rev4wi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev4.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 28)
+ ret i64 %tmp
+}
+
+define i64 @rev2wi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: rev2wi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev2.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 30)
+ ret i64 %tmp
+}
+
+define i64 @revwi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: revwi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 31)
+ ret i64 %tmp
+}
+
+define i64 @rev32i64(i64 %a) nounwind {
+; RV64ZBP-LABEL: rev32i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev32 a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 32)
+ ret i64 %tmp
+}
+
+define i64 @rev16i64(i64 %a) nounwind {
+; RV64ZBP-LABEL: rev16i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev16 a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 48)
+ ret i64 %tmp
+}
+
+define i64 @rev8i64(i64 %a) nounwind {
+; RV64ZBP-LABEL: rev8i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev8 a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 56)
+ ret i64 %tmp
+}
+
+define i64 @rev4i64(i64 %a) nounwind {
+; RV64ZBP-LABEL: rev4i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev4 a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 60)
+ ret i64 %tmp
+}
+
+define i64 @rev2i64(i64 %a) nounwind {
+; RV64ZBP-LABEL: rev2i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev2 a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 62)
+ ret i64 %tmp
+}
+
+define i64 @revi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: revi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 63)
+ ret i64 %tmp
+}
+
declare i64 @llvm.riscv.gorc.i64(i64 %a, i64 %b)
define i64 @gorc64(i64 %a, i64 %b) nounwind {
diff --git a/llvm/test/CodeGen/RISCV/rv64zbp.ll b/llvm/test/CodeGen/RISCV/rv64zbp.ll
index 6a4376409fab5..552991076629e 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbp.ll
@@ -1510,6 +1510,194 @@ define i64 @grev8_i64(i64 %a) nounwind {
ret i64 %or
}
+define signext i32 @grev12_i32(i32 signext %a) nounwind {
+; RV64I-LABEL: grev12_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slliw a1, a0, 4
+; RV64I-NEXT: lui a2, 986895
+; RV64I-NEXT: addiw a2, a2, 240
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: srli a0, a0, 4
+; RV64I-NEXT: lui a2, 61681
+; RV64I-NEXT: addiw a2, a2, -241
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: slliw a1, a0, 8
+; RV64I-NEXT: lui a2, 1044496
+; RV64I-NEXT: addiw a2, a2, -256
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: srli a0, a0, 8
+; RV64I-NEXT: lui a2, 4080
+; RV64I-NEXT: addiw a2, a2, 255
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: ret
+;
+; RV64ZBP-LABEL: grev12_i32:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: greviw a0, a0, 12
+; RV64ZBP-NEXT: ret
+ %and1 = shl i32 %a, 4
+ %shl1 = and i32 %and1, -252645136
+ %and1b = lshr i32 %a, 4
+ %shr1 = and i32 %and1b, 252645135
+ %or1 = or i32 %shl1, %shr1
+ %and2 = shl i32 %or1, 8
+ %shl2 = and i32 %and2, -16711936
+ %and2b = lshr i32 %or1, 8
+ %shr2 = and i32 %and2b, 16711935
+ %or2 = or i32 %shl2, %shr2
+ ret i32 %or2
+}
+
+define i64 @grev12_i64(i64 %a) nounwind {
+; RV64I-LABEL: grev12_i64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, %hi(.LCPI44_0)
+; RV64I-NEXT: ld a1, %lo(.LCPI44_0)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI44_1)
+; RV64I-NEXT: ld a2, %lo(.LCPI44_1)(a2)
+; RV64I-NEXT: slli a3, a0, 4
+; RV64I-NEXT: and a1, a3, a1
+; RV64I-NEXT: srli a0, a0, 4
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: lui a1, %hi(.LCPI44_2)
+; RV64I-NEXT: ld a1, %lo(.LCPI44_2)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI44_3)
+; RV64I-NEXT: ld a2, %lo(.LCPI44_3)(a2)
+; RV64I-NEXT: slli a3, a0, 8
+; RV64I-NEXT: and a1, a3, a1
+; RV64I-NEXT: srli a0, a0, 8
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: ret
+;
+; RV64ZBP-LABEL: grev12_i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev4.h a0, a0
+; RV64ZBP-NEXT: ret
+ %and1 = shl i64 %a, 4
+ %shl1 = and i64 %and1, -1085102592571150096
+ %and1b = lshr i64 %a, 4
+ %shr1 = and i64 %and1b, 1085102592571150095
+ %or1 = or i64 %shl1, %shr1
+ %and2 = shl i64 %or1, 8
+ %shl2 = and i64 %and2, -71777214294589696
+ %and2b = lshr i64 %or1, 8
+ %shr2 = and i64 %and2b, 71777214294589695
+ %or2 = or i64 %shl2, %shr2
+ ret i64 %or2
+}
+
+define signext i32 @grev14_i32(i32 signext %a) nounwind {
+; RV64I-LABEL: grev14_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slliw a1, a0, 2
+; RV64I-NEXT: lui a2, 838861
+; RV64I-NEXT: addiw a2, a2, -820
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: srli a0, a0, 2
+; RV64I-NEXT: lui a2, 209715
+; RV64I-NEXT: addiw a2, a2, 819
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: slliw a1, a0, 4
+; RV64I-NEXT: lui a2, 986895
+; RV64I-NEXT: addiw a2, a2, 240
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: srli a0, a0, 4
+; RV64I-NEXT: lui a2, 61681
+; RV64I-NEXT: addiw a2, a2, -241
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: slliw a1, a0, 8
+; RV64I-NEXT: lui a2, 1044496
+; RV64I-NEXT: addiw a2, a2, -256
+; RV64I-NEXT: and a1, a1, a2
+; RV64I-NEXT: srli a0, a0, 8
+; RV64I-NEXT: lui a2, 4080
+; RV64I-NEXT: addiw a2, a2, 255
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: ret
+;
+; RV64ZBP-LABEL: grev14_i32:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: greviw a0, a0, 14
+; RV64ZBP-NEXT: ret
+ %and1 = shl i32 %a, 2
+ %shl1 = and i32 %and1, -858993460
+ %and1b = lshr i32 %a, 2
+ %shr1 = and i32 %and1b, 858993459
+ %or1 = or i32 %shl1, %shr1
+ %and2 = shl i32 %or1, 4
+ %shl2 = and i32 %and2, -252645136
+ %and2b = lshr i32 %or1, 4
+ %shr2 = and i32 %and2b, 252645135
+ %or2 = or i32 %shl2, %shr2
+ %and3 = shl i32 %or2, 8
+ %shl3 = and i32 %and3, -16711936
+ %and3b = lshr i32 %or2, 8
+ %shr3 = and i32 %and3b, 16711935
+ %or3 = or i32 %shl3, %shr3
+ ret i32 %or3
+}
+
+define i64 @grev14_i64(i64 %a) nounwind {
+; RV64I-LABEL: grev14_i64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, %hi(.LCPI46_0)
+; RV64I-NEXT: ld a1, %lo(.LCPI46_0)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI46_1)
+; RV64I-NEXT: ld a2, %lo(.LCPI46_1)(a2)
+; RV64I-NEXT: slli a3, a0, 2
+; RV64I-NEXT: and a1, a3, a1
+; RV64I-NEXT: srli a0, a0, 2
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: lui a1, %hi(.LCPI46_2)
+; RV64I-NEXT: ld a1, %lo(.LCPI46_2)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI46_3)
+; RV64I-NEXT: ld a2, %lo(.LCPI46_3)(a2)
+; RV64I-NEXT: slli a3, a0, 4
+; RV64I-NEXT: and a1, a3, a1
+; RV64I-NEXT: srli a0, a0, 4
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: lui a1, %hi(.LCPI46_4)
+; RV64I-NEXT: ld a1, %lo(.LCPI46_4)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI46_5)
+; RV64I-NEXT: ld a2, %lo(.LCPI46_5)(a2)
+; RV64I-NEXT: slli a3, a0, 8
+; RV64I-NEXT: and a1, a3, a1
+; RV64I-NEXT: srli a0, a0, 8
+; RV64I-NEXT: and a0, a0, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: ret
+;
+; RV64ZBP-LABEL: grev14_i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: rev2.h a0, a0
+; RV64ZBP-NEXT: ret
+ %and1 = shl i64 %a, 2
+ %shl1 = and i64 %and1, -3689348814741910324
+ %and1b = lshr i64 %a, 2
+ %shr1 = and i64 %and1b, 3689348814741910323
+ %or1 = or i64 %shl1, %shr1
+ %and2 = shl i64 %or1, 4
+ %shl2 = and i64 %and2, -1085102592571150096
+ %and2b = lshr i64 %or1, 4
+ %shr2 = and i64 %and2b, 1085102592571150095
+ %or2 = or i64 %shl2, %shr2
+ %and3 = shl i64 %or2, 8
+ %shl3 = and i64 %and3, -71777214294589696
+ %and3b = lshr i64 %or2, 8
+ %shr3 = and i64 %and3b, 71777214294589695
+ %or3 = or i64 %shl3, %shr3
+ ret i64 %or3
+}
+
define signext i32 @grev16_i32(i32 signext %a) nounwind {
; RV64I-LABEL: grev16_i32:
; RV64I: # %bb.0:
@@ -1653,19 +1841,19 @@ define signext i32 @grev3b_i32(i32 signext %a) nounwind {
define i64 @grev3b_i64(i64 %a) nounwind {
; RV64I-LABEL: grev3b_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, %hi(.LCPI49_0)
-; RV64I-NEXT: ld a1, %lo(.LCPI49_0)(a1)
-; RV64I-NEXT: lui a2, %hi(.LCPI49_1)
-; RV64I-NEXT: ld a2, %lo(.LCPI49_1)(a2)
+; RV64I-NEXT: lui a1, %hi(.LCPI53_0)
+; RV64I-NEXT: ld a1, %lo(.LCPI53_0)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI53_1)
+; RV64I-NEXT: ld a2, %lo(.LCPI53_1)(a2)
; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
-; RV64I-NEXT: lui a1, %hi(.LCPI49_2)
-; RV64I-NEXT: ld a1, %lo(.LCPI49_2)(a1)
-; RV64I-NEXT: lui a2, %hi(.LCPI49_3)
-; RV64I-NEXT: ld a2, %lo(.LCPI49_3)(a2)
+; RV64I-NEXT: lui a1, %hi(.LCPI53_2)
+; RV64I-NEXT: ld a1, %lo(.LCPI53_2)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI53_3)
+; RV64I-NEXT: ld a2, %lo(.LCPI53_3)(a2)
; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: srli a0, a0, 1
@@ -1745,19 +1933,19 @@ define signext i32 @grev2b_i32(i32 signext %a) nounwind {
define i64 @grev2b_i64(i64 %a) nounwind {
; RV64I-LABEL: grev2b_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, %hi(.LCPI51_0)
-; RV64I-NEXT: ld a1, %lo(.LCPI51_0)(a1)
-; RV64I-NEXT: lui a2, %hi(.LCPI51_1)
-; RV64I-NEXT: ld a2, %lo(.LCPI51_1)(a2)
+; RV64I-NEXT: lui a1, %hi(.LCPI55_0)
+; RV64I-NEXT: ld a1, %lo(.LCPI55_0)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI55_1)
+; RV64I-NEXT: ld a2, %lo(.LCPI55_1)(a2)
; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a3, a3, a1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a3, a0
-; RV64I-NEXT: lui a3, %hi(.LCPI51_2)
-; RV64I-NEXT: ld a3, %lo(.LCPI51_2)(a3)
-; RV64I-NEXT: lui a4, %hi(.LCPI51_3)
-; RV64I-NEXT: ld a4, %lo(.LCPI51_3)(a4)
+; RV64I-NEXT: lui a3, %hi(.LCPI55_2)
+; RV64I-NEXT: ld a3, %lo(.LCPI55_2)(a3)
+; RV64I-NEXT: lui a4, %hi(.LCPI55_3)
+; RV64I-NEXT: ld a4, %lo(.LCPI55_3)(a4)
; RV64I-NEXT: slli a5, a0, 2
; RV64I-NEXT: and a3, a5, a3
; RV64I-NEXT: srli a0, a0, 2
@@ -1856,19 +2044,19 @@ define signext i32 @grev0_i32(i32 signext %a) nounwind {
define i64 @grev0_i64(i64 %a) nounwind {
; RV64I-LABEL: grev0_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, %hi(.LCPI53_0)
-; RV64I-NEXT: ld a1, %lo(.LCPI53_0)(a1)
-; RV64I-NEXT: lui a2, %hi(.LCPI53_1)
-; RV64I-NEXT: ld a2, %lo(.LCPI53_1)(a2)
+; RV64I-NEXT: lui a1, %hi(.LCPI57_0)
+; RV64I-NEXT: ld a1, %lo(.LCPI57_0)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI57_1)
+; RV64I-NEXT: ld a2, %lo(.LCPI57_1)(a2)
; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a3, a3, a1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a3, a0
-; RV64I-NEXT: lui a3, %hi(.LCPI53_2)
-; RV64I-NEXT: ld a3, %lo(.LCPI53_2)(a3)
-; RV64I-NEXT: lui a4, %hi(.LCPI53_3)
-; RV64I-NEXT: ld a4, %lo(.LCPI53_3)(a4)
+; RV64I-NEXT: lui a3, %hi(.LCPI57_2)
+; RV64I-NEXT: ld a3, %lo(.LCPI57_2)(a3)
+; RV64I-NEXT: lui a4, %hi(.LCPI57_3)
+; RV64I-NEXT: ld a4, %lo(.LCPI57_3)(a4)
; RV64I-NEXT: slli a5, a0, 2
; RV64I-NEXT: and a5, a5, a3
; RV64I-NEXT: srli a0, a0, 2
@@ -2263,22 +2451,22 @@ define i64 @bitreverse_i64(i64 %a) nounwind {
; RV64I-NEXT: and a3, a4, a3
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a3
-; RV64I-NEXT: lui a3, %hi(.LCPI64_0)
-; RV64I-NEXT: ld a3, %lo(.LCPI64_0)(a3)
+; RV64I-NEXT: lui a3, %hi(.LCPI68_0)
+; RV64I-NEXT: ld a3, %lo(.LCPI68_0)(a3)
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: and a0, a0, a3
-; RV64I-NEXT: lui a2, %hi(.LCPI64_1)
-; RV64I-NEXT: ld a2, %lo(.LCPI64_1)(a2)
+; RV64I-NEXT: lui a2, %hi(.LCPI68_1)
+; RV64I-NEXT: ld a2, %lo(.LCPI68_1)(a2)
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: lui a2, %hi(.LCPI64_2)
-; RV64I-NEXT: ld a2, %lo(.LCPI64_2)(a2)
+; RV64I-NEXT: lui a2, %hi(.LCPI68_2)
+; RV64I-NEXT: ld a2, %lo(.LCPI68_2)(a2)
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1
@@ -2386,20 +2574,20 @@ define i32 @bitreverse_bswap_i32(i32 %a) {
define i64 @bitreverse_bswap_i64(i64 %a) {
; RV64I-LABEL: bitreverse_bswap_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, %hi(.LCPI68_0)
-; RV64I-NEXT: ld a1, %lo(.LCPI68_0)(a1)
+; RV64I-NEXT: lui a1, %hi(.LCPI72_0)
+; RV64I-NEXT: ld a1, %lo(.LCPI72_0)(a1)
; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: lui a1, %hi(.LCPI68_1)
-; RV64I-NEXT: ld a1, %lo(.LCPI68_1)(a1)
+; RV64I-NEXT: lui a1, %hi(.LCPI72_1)
+; RV64I-NEXT: ld a1, %lo(.LCPI72_1)(a1)
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: srli a2, a0, 2
; RV64I-NEXT: and a2, a2, a1
; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: lui a1, %hi(.LCPI68_2)
-; RV64I-NEXT: ld a1, %lo(.LCPI68_2)(a1)
+; RV64I-NEXT: lui a1, %hi(.LCPI72_2)
+; RV64I-NEXT: ld a1, %lo(.LCPI72_2)(a1)
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: srli a2, a0, 1
@@ -2453,14 +2641,14 @@ define signext i32 @shfl1_i32(i32 signext %a, i32 signext %b) nounwind {
define i64 @shfl1_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: shfl1_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, %hi(.LCPI70_1)
-; RV64I-NEXT: ld a1, %lo(.LCPI70_1)(a1)
-; RV64I-NEXT: lui a2, %hi(.LCPI70_0)
-; RV64I-NEXT: ld a2, %lo(.LCPI70_0)(a2)
+; RV64I-NEXT: lui a1, %hi(.LCPI74_1)
+; RV64I-NEXT: ld a1, %lo(.LCPI74_1)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI74_0)
+; RV64I-NEXT: ld a2, %lo(.LCPI74_0)(a2)
; RV64I-NEXT: slli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
-; RV64I-NEXT: lui a3, %hi(.LCPI70_2)
-; RV64I-NEXT: ld a3, %lo(.LCPI70_2)(a3)
+; RV64I-NEXT: lui a3, %hi(.LCPI74_2)
+; RV64I-NEXT: ld a3, %lo(.LCPI74_2)(a3)
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a0, a0, 1
@@ -2517,14 +2705,14 @@ define signext i32 @shfl2_i32(i32 signext %a, i32 signext %b) nounwind {
define i64 @shfl2_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: shfl2_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, %hi(.LCPI72_1)
-; RV64I-NEXT: ld a1, %lo(.LCPI72_1)(a1)
-; RV64I-NEXT: lui a2, %hi(.LCPI72_0)
-; RV64I-NEXT: ld a2, %lo(.LCPI72_0)(a2)
+; RV64I-NEXT: lui a1, %hi(.LCPI76_1)
+; RV64I-NEXT: ld a1, %lo(.LCPI76_1)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI76_0)
+; RV64I-NEXT: ld a2, %lo(.LCPI76_0)(a2)
; RV64I-NEXT: slli a3, a0, 2
; RV64I-NEXT: and a1, a3, a1
-; RV64I-NEXT: lui a3, %hi(.LCPI72_2)
-; RV64I-NEXT: ld a3, %lo(.LCPI72_2)(a3)
+; RV64I-NEXT: lui a3, %hi(.LCPI76_2)
+; RV64I-NEXT: ld a3, %lo(.LCPI76_2)(a3)
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a0, a0, 2
@@ -2581,13 +2769,13 @@ define signext i32 @shfl4_i32(i32 signext %a, i32 signext %b) nounwind {
define i64 @shfl4_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: shfl4_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, %hi(.LCPI74_0)
-; RV64I-NEXT: ld a1, %lo(.LCPI74_0)(a1)
-; RV64I-NEXT: lui a2, %hi(.LCPI74_1)
-; RV64I-NEXT: ld a2, %lo(.LCPI74_1)(a2)
+; RV64I-NEXT: lui a1, %hi(.LCPI78_0)
+; RV64I-NEXT: ld a1, %lo(.LCPI78_0)(a1)
+; RV64I-NEXT: lui a2, %hi(.LCPI78_1)
+; RV64I-NEXT: ld a2, %lo(.LCPI78_1)(a2)
; RV64I-NEXT: slli a3, a0, 4
-; RV64I-NEXT: lui a4, %hi(.LCPI74_2)
-; RV64I-NEXT: ld a4, %lo(.LCPI74_2)(a4)
+; RV64I-NEXT: lui a4, %hi(.LCPI78_2)
+; RV64I-NEXT: ld a4, %lo(.LCPI78_2)(a4)
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: srli a0, a0, 4
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