[compiler-rt] fc0bd3c - [libFuzzer] Refactor GetNextInstructionPc/GetPreviousInstructionPc

[Fangrui Song via llvm-commits]

Author: Fangrui Song
Date: 2022-02-22T16:25:57-08:00
New Revision: fc0bd3c2cee929ffbd75b5cca486f4c77f7d5c59

URL: https://github.com/llvm/llvm-project/commit/fc0bd3c2cee929ffbd75b5cca486f4c77f7d5c59
DIFF: https://github.com/llvm/llvm-project/commit/fc0bd3c2cee929ffbd75b5cca486f4c77f7d5c59.diff

LOG: [libFuzzer] Refactor GetNextInstructionPc/GetPreviousInstructionPc

Port the change to compiler-rt/lib/fuzzer/FuzzerTracePC.cpp .
Update RISCV to use PC-2: this is coarse (C extension may be disabled) but
sufficient for pure symbolization purpose.

The commit is separate from D120362 so that bisecting/reverting is easier.

Added: 
    

Modified: 
    compiler-rt/lib/fuzzer/FuzzerTracePC.cpp

Removed: 
    


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diff  --git a/compiler-rt/lib/fuzzer/FuzzerTracePC.cpp b/compiler-rt/lib/fuzzer/FuzzerTracePC.cpp
index af8d1ce50f3fb..f12f7aa61bc4a 100644
--- a/compiler-rt/lib/fuzzer/FuzzerTracePC.cpp
+++ b/compiler-rt/lib/fuzzer/FuzzerTracePC.cpp
@@ -133,13 +133,14 @@ inline ALWAYS_INLINE uintptr_t GetPreviousInstructionPc(uintptr_t PC) {
   // so we return (pc-2) in that case in order to be safe.
   // For A32 mode we return (pc-4) because all instructions are 32 bit long.
   return (PC - 3) & (~1);
-#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__aarch64__)
-  // PCs are always 4 byte aligned.
-  return PC - 4;
 #elif defined(__sparc__) || defined(__mips__)
   return PC - 8;
-#else
+#elif defined(__riscv__)
+  return PC - 2;
+#elif defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
   return PC - 1;
+#else
+  return PC - 4;
 #endif
 }