[PATCH] D120355: [AMDGPU] Code improvements

[Aakanksha Patil via Phabricator via llvm-commits]

aakanksha555 created this revision.
aakanksha555 added reviewers: msearles, kzhuravl.
Herald added subscribers: foad, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, arsenm.
aakanksha555 requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

Fix for CodeQL AMD queries


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120355

Files:
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp
  llvm/tools/llvm-pdbutil/StreamUtil.cpp
  llvm/utils/TableGen/X86RecognizableInstr.cpp


Index: llvm/utils/TableGen/X86RecognizableInstr.cpp
===================================================================
--- llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -835,7 +835,7 @@
   if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC ||
       Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC ||
       Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) {
-    unsigned Count = Form == X86Local::AddRegFrm ? 8 : 16;
+    uint8_t Count = Form == X86Local::AddRegFrm ? 8 : 16;
     assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned");
 
     uint8_t currentOpcode;
Index: llvm/tools/llvm-pdbutil/StreamUtil.cpp
===================================================================
--- llvm/tools/llvm-pdbutil/StreamUtil.cpp
+++ llvm/tools/llvm-pdbutil/StreamUtil.cpp
@@ -95,7 +95,7 @@
   }
 
   Streams.resize(StreamCount);
-  for (uint16_t StreamIdx = 0; StreamIdx < StreamCount; ++StreamIdx) {
+  for (uint32_t StreamIdx = 0; StreamIdx < StreamCount; ++StreamIdx) {
     if (StreamIdx == OldMSFDirectory)
       Streams[StreamIdx] =
           stream(StreamPurpose::Other, "Old MSF Directory", StreamIdx);
Index: llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp
===================================================================
--- llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp
+++ llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp
@@ -389,7 +389,7 @@
   uint32_t StreamCount = getPdb().getNumStreams();
   uint32_t MaxStreamSize = getPdb().getMaxStreamSize();
 
-  for (uint16_t StreamIdx = 0; StreamIdx < StreamCount; ++StreamIdx) {
+  for (uint32_t StreamIdx = 0; StreamIdx < StreamCount; ++StreamIdx) {
     P.formatLine(
         "Stream {0} ({1} bytes): [{2}]",
         fmt_align(StreamIdx, AlignStyle::Right, NumDigits(StreamCount)),
Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -357,7 +357,7 @@
   static auto InitializeSubRegFromChannelTableOnce = [this]() {
     for (auto &Row : SubRegFromChannelTable)
       Row.fill(AMDGPU::NoSubRegister);
-    for (uint16_t Idx = 1; Idx < getNumSubRegIndices(); ++Idx) {
+    for (unsigned Idx = 1; Idx < getNumSubRegIndices(); ++Idx) {
       unsigned Width = AMDGPUSubRegIdxRanges[Idx].Size / 32;
       unsigned Offset = AMDGPUSubRegIdxRanges[Idx].Offset / 32;
       assert(Width < SubRegFromChannelTableWidthMap.size());


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