[PATCH] D120300: [RISCV] Pre-commit tests for vcpop and vfirst with VL=0

[Chenbing.Zheng via Phabricator via llvm-commits]

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Pre-commit tests


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120300

Files:
  llvm/test/CodeGen/RISCV/rvv/vcpop.ll
  llvm/test/CodeGen/RISCV/rvv/vfirst.ll


Index: llvm/test/CodeGen/RISCV/rvv/vfirst.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vfirst.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfirst.ll
@@ -21,6 +21,20 @@
   ret iXLen %a
 }
 
+define iXLen @intrinsic_vfirst_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind {
+; CHECK-LABEL: intrinsic_vfirst_m_nxv1i1_zero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
+; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    ret
+entry:
+  %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1(
+    <vscale x 1 x i1> %0,
+    iXLen 0)
+
+  ret iXLen %a
+}
+
 declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
   <vscale x 1 x i1>,
   <vscale x 1 x i1>,
@@ -43,6 +57,23 @@
   ret iXLen %a
 }
 
+define iXLen @intrinsic_vfirst_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
+; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv1i1_zero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v9, v0
+; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vfirst.m a0, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    iXLen 0)
+
+  ret iXLen %a
+}
+
 declare iXLen @llvm.riscv.vfirst.iXLen.nxv2i1(
   <vscale x 2 x i1>,
   iXLen);
Index: llvm/test/CodeGen/RISCV/rvv/vcpop.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vcpop.ll
+++ llvm/test/CodeGen/RISCV/rvv/vcpop.ll
@@ -21,6 +21,20 @@
   ret iXLen %a
 }
 
+define iXLen @intrinsic_vcpop_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind {
+; CHECK-LABEL: intrinsic_vcpop_m_nxv1i1_zero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
+; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    ret
+entry:
+  %a = call iXLen @llvm.riscv.vcpop.iXLen.nxv1i1(
+    <vscale x 1 x i1> %0,
+    iXLen 0)
+
+  ret iXLen %a
+}
+
 declare iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
   <vscale x 1 x i1>,
   <vscale x 1 x i1>,
@@ -43,6 +57,23 @@
   ret iXLen %a
 }
 
+define iXLen @intrinsic_vcpop_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
+; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv1i1_zero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v9, v0
+; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vcpop.m a0, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    iXLen 0)
+
+  ret iXLen %a
+}
+
 declare iXLen @llvm.riscv.vcpop.iXLen.nxv2i1(
   <vscale x 2 x i1>,
   iXLen);


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