[PATCH] D120112: Teach the AArch64 backend to instruction select the BCAX instruction.

[Owen Anderson via Phabricator via llvm-commits]

resistor updated this revision to Diff 410447.
resistor added a comment.

Fix operand order.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120112/new/

https://reviews.llvm.org/D120112

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/bcax.ll


Index: llvm/test/CodeGen/AArch64/bcax.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/bcax.ll
@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --extra_scrub
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
+
+define <4 x i32> @bcax_32x4(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) {
+; SHA3-LABEL: bcax_32x4:
+; SHA3:       // %bb.0:
+; SHA3-NEXT:    bcax v0.16b, v2.16b, v0.16b, v1.16b
+; SHA3-NEXT:    ret
+;
+; NOSHA3-LABEL: bcax_32x4:
+; NOSHA3:       // %bb.0:
+; NOSHA3-NEXT:    bic v0.16b, v0.16b, v1.16b
+; NOSHA3-NEXT:    eor v0.16b, v0.16b, v2.16b
+; NOSHA3-NEXT:    ret
+  %4 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %5 = and <4 x i32> %4, %0
+  %6 = xor <4 x i32> %5, %2
+  ret <4 x i32> %6
+}
+
+define <8 x i16> @bcax_16x8(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) {
+; SHA3-LABEL: bcax_16x8:
+; SHA3:       // %bb.0:
+; SHA3-NEXT:    bcax v0.16b, v2.16b, v0.16b, v1.16b
+; SHA3-NEXT:    ret
+;
+; NOSHA3-LABEL: bcax_16x8:
+; NOSHA3:       // %bb.0:
+; NOSHA3-NEXT:    bic v0.16b, v0.16b, v1.16b
+; NOSHA3-NEXT:    eor v0.16b, v0.16b, v2.16b
+; NOSHA3-NEXT:    ret
+  %4 = xor <8 x i16> %1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+  %5 = and <8 x i16> %4, %0
+  %6 = xor <8 x i16> %5, %2
+  ret <8 x i16> %6
+}
+
+define <16 x i8> @bcax_8x16(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) {
+; SHA3-LABEL: bcax_8x16:
+; SHA3:       // %bb.0:
+; SHA3-NEXT:    bcax v0.16b, v2.16b, v0.16b, v1.16b
+; SHA3-NEXT:    ret
+;
+; NOSHA3-LABEL: bcax_8x16:
+; NOSHA3:       // %bb.0:
+; NOSHA3-NEXT:    bic v0.16b, v0.16b, v1.16b
+; NOSHA3-NEXT:    eor v0.16b, v0.16b, v2.16b
+; NOSHA3-NEXT:    ret
+  %4 = xor <16 x i8> %1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %5 = and <16 x i8> %4, %0
+  %6 = xor <16 x i8> %5, %2
+  ret <16 x i8> %6
+}
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1024,6 +1024,15 @@
 def : EOR3_pattern<v4i32>;
 def : EOR3_pattern<v2i64>;
 
+class BCAX_pattern<ValueType VecTy>
+  : Pat<(xor (VecTy V128:$Vn), (and (VecTy V128:$Vm), (vnot (VecTy V128:$Va)))),
+        (BCAX (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
+
+def : BCAX_pattern<v16i8>;
+def : BCAX_pattern<v8i16>;
+def : BCAX_pattern<v4i32>;
+def : BCAX_pattern<v2i64>;
+
 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v16i8>;
 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v8i16>;
 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v4i32>;


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