[PATCH] D120286: AMDGPU: Don't use unreachable on stores to unhandled address space

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 21 15:31:30 PST 2022


arsenm created this revision.
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For stores to constant address space, this will now consistently hit a
selection error instead of hitting unreachable in an asserts build.

      

I'm not sure what we should really do here. We could either just
codegen as if it were global, delete the instruction, or declare the
IR invalid (we really should have a target IR verifier to enforce it).


https://reviews.llvm.org/D120286

Files:
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/store-to-constant-error.ll


Index: llvm/test/CodeGen/AMDGPU/store-to-constant-error.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/store-to-constant-error.ll
@@ -0,0 +1,10 @@
+; RUN: not --crash llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o /dev/null %s 2>&1 | FileCheck -check-prefix=SDAG %s
+; RUN: not --crash llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o /dev/null %s 2>&1 | FileCheck -check-prefix=GISEL %s
+
+; SDAG: LLVM ERROR: Cannot select: t{{[0-9]+}}: ch = store<(store (s32) into %ir.ptr.load, addrspace 4)>
+; GISEL: LLVM ERROR: cannot select: G_STORE %{{[0-9]+}}:vgpr(s32), %{{[0-9]+}}:vgpr(p4) :: (store (s32) into %ir.ptr.load, addrspace 4) (in function: store_to_constant_i32)
+define amdgpu_kernel void @store_to_constant_i32(i32 addrspace(4)* %ptr) {
+bb:
+  store i32 1, i32 addrspace(4)* %ptr, align 4
+  ret void
+}
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -9043,9 +9043,10 @@
     }
 
     return SDValue();
-  } else {
-    llvm_unreachable("unhandled address space");
   }
+
+  // Probably an invalid store. If so we'll end up emitting a selection error.
+  return SDValue();
 }
 
 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {


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