[PATCH] D119475: [AMDGPU] Add scheduler pass to rematerialize trivial defs

[Vang Thao via Phabricator via llvm-commits]

vangthao marked 2 inline comments as done.
vangthao added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir:2653
+    undef %21.sub0:vreg_128 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode
+    %21.sub1:vreg_128 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode, implicit-def $m0
+
----------------
rampitec wrote:
> Do you have a similar test with sub1 and sub0 defined which would be sinkable if not subreg use?
Added test: test_no_sink_two_subregs_in_def_block.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119475/new/

https://reviews.llvm.org/D119475