[PATCH] D120250: [RISCV] Optimize tail agnostic vmv.s.x which don't need to select tail value.

[Zakk Chen via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf7dfc5d1af6c: [RISCV] Optimize tail agnostic vmv.s.x which don't need to select tail value. (authored by khchen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120250/new/

https://reviews.llvm.org/D120250

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll


Index: llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
+++ llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
@@ -1124,9 +1124,6 @@
 ; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    vlse64.v v8, (a0), zero
-; RV32-NEXT:    vid.v v9
-; RV32-NEXT:    vmseq.vi v0, v9, 0
-; RV32-NEXT:    vmerge.vvm v8, v8, v8, v0
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4757,6 +4757,8 @@
     SDValue VL = getVLOperand(Op);
 
     SDValue SplattedVal = splatSplitI64WithVL(DL, VT, SDValue(), Scalar, VL, DAG);
+    if (Op.getOperand(1).isUndef())
+      return SplattedVal;
     SDValue SplattedIdx =
         DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, DAG.getUNDEF(VT),
                     DAG.getConstant(0, DL, MVT::i32), VL);


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