[llvm] f7dfc5d - [RISCV] Optimize tail agnostic vmv.s.x which don't need to select tail value.

[Zakk Chen via llvm-commits]

Author: Zakk Chen
Date: 2022-02-21T14:53:37-08:00
New Revision: f7dfc5d1af6cfd1f9b6f2ac2d11f6074e8425ba7

URL: https://github.com/llvm/llvm-project/commit/f7dfc5d1af6cfd1f9b6f2ac2d11f6074e8425ba7
DIFF: https://github.com/llvm/llvm-project/commit/f7dfc5d1af6cfd1f9b6f2ac2d11f6074e8425ba7.diff

LOG: [RISCV] Optimize tail agnostic vmv.s.x which don't need to select tail value.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D120250

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4395c139b7220..a54ae084cfe6b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4757,6 +4757,8 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     SDValue VL = getVLOperand(Op);
 
     SDValue SplattedVal = splatSplitI64WithVL(DL, VT, SDValue(), Scalar, VL, DAG);
+    if (Op.getOperand(1).isUndef())
+      return SplattedVal;
     SDValue SplattedIdx =
         DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, DAG.getUNDEF(VT),
                     DAG.getConstant(0, DL, MVT::i32), VL);

diff  --git a/llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll b/llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
index 65b225ede7152..e7a11c6a930dd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
@@ -1124,9 +1124,6 @@ define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64(i64 %0, iXLen %1) nounwin
 ; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    vlse64.v v8, (a0), zero
-; RV32-NEXT:    vid.v v9
-; RV32-NEXT:    vmseq.vi v0, v9, 0
-; RV32-NEXT:    vmerge.vvm v8, v8, v8, v0
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;