[PATCH] D119973: RegAllocGreedy: Fix last chance recolor assert in impossible case

Mon Feb 21 09:27:10 PST 2022

arsenm added a comment.

In D119973#3335190 <https://reviews.llvm.org/D119973#3335190>, @uabelho wrote:

> In a failing example we have a bundle like this with heavy register use:
>
>   BUNDLE [...] {
>     inst1 %234:Aquad
>     inst1 %235:Aquad
>     undef %235.sub0:Aquad = inst2 %211:A, %237.sub0:Aquad
>     undef %235.sub1:Aquad = inst2 %226:A, %237.sub1:Aquad
>     undef %235.sub2:Aquad = inst2 %229:A, %237.sub0:Aquad
>     undef %235.sub3:Aquad = inst2 %232:A, %237.sub1:Aquad
>   }

Can you fill out more context with the surrounding instructions + ranges? Theoretically I can reconstruct the same scenario using -stress-regalloc

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  https://reviews.llvm.org/D119973/new/

https://reviews.llvm.org/D119973