[PATCH] D120193: [X86][SSE] Attempt to lower vec_reduce_add patterns with PSADBW for zero-extended vXi8 sources

[Phoebe Wang via Phabricator via llvm-commits]

pengfei added a comment.

Clang-format the code.



================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:43062-43064
+    Rdx = DAG.getNode(ISD::TRUNCATE, DL, ByteVT, Rdx);
+    if (ByteVT.getSizeInBits() < 128)
+      Rdx = WidenToV16I8(Rdx, true);
----------------
I don't understand the code quite well, some doubts:
1. If the source are known <= 255, why do we need truncate it. Should be better to bitcast directly?
2. If the ByteVT < 128, why don't we widen it with undef and return the value of lane 0 after PSADBW?


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https://reviews.llvm.org/D120193