[llvm] 9a547e7 - [StableHashing] Hash vregs with multiple defs

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2022-02-21T10:26:34Z
New Revision: 9a547e7009f7502f6e32361f6e8812837a30576f

URL: https://github.com/llvm/llvm-project/commit/9a547e7009f7502f6e32361f6e8812837a30576f
DIFF: https://github.com/llvm/llvm-project/commit/9a547e7009f7502f6e32361f6e8812837a30576f.diff

LOG: [StableHashing] Hash vregs with multiple defs

This allows stableHashValue to be used on Machine IR that is
not in SSA form.

Differential Revision: https://reviews.llvm.org/D120121

Added: 
    

Modified: 
    llvm/lib/CodeGen/MachineStableHash.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/MachineStableHash.cpp b/llvm/lib/CodeGen/MachineStableHash.cpp
index 0803c2b8b85a3..6b213f8d0bdfc 100644
--- a/llvm/lib/CodeGen/MachineStableHash.cpp
+++ b/llvm/lib/CodeGen/MachineStableHash.cpp
@@ -64,7 +64,10 @@ stable_hash llvm::stableHashValue(const MachineOperand &MO) {
   case MachineOperand::MO_Register:
     if (Register::isVirtualRegister(MO.getReg())) {
       const MachineRegisterInfo &MRI = MO.getParent()->getMF()->getRegInfo();
-      return MRI.getVRegDef(MO.getReg())->getOpcode();
+      SmallVector<unsigned> DefOpcodes;
+      for (auto &Def : MRI.def_instructions(MO.getReg()))
+        DefOpcodes.push_back(Def.getOpcode());
+      return hash_combine_range(DefOpcodes.begin(), DefOpcodes.end());
     }
 
     // Register operands don't have target flags.