[llvm] 2e15303 - [RISCV] Add tests for SHFLI and UNSHFLI aliases in Zbp extension
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 21 02:10:44 PST 2022
Author: Lian Wang
Date: 2022-02-21T10:10:32Z
New Revision: 2e153038b4a7003f1032ab0340c4e9cce3a066cd
URL: https://github.com/llvm/llvm-project/commit/2e153038b4a7003f1032ab0340c4e9cce3a066cd
DIFF: https://github.com/llvm/llvm-project/commit/2e153038b4a7003f1032ab0340c4e9cce3a066cd.diff
LOG: [RISCV] Add tests for SHFLI and UNSHFLI aliases in Zbp extension
Supplement tests alias of SHFLI and UNSHFLI instructions.
RV32: zip8/zip4/zip2/unzip8/unzip4/unzip2
RV64: zip8.w/zip4.w/zip2.w/zip.w/zip8/zip4/zip2/zip/
unzip8.w/unzip4.w/unzip2.w/unzip.w/unzip8/unzip4/unzip2/unzip
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D120015
Added:
Modified:
llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
index 4f1dd3d588844..816a27b2be4da 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll
@@ -92,6 +92,24 @@ define i32 @shfli32(i32 %a) nounwind {
ret i32 %tmp
}
+define i32 @zip4i32(i32 %a) nounwind {
+; RV32ZBP-LABEL: zip4i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: zip4 a0, a0
+; RV32ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 12)
+ ret i32 %tmp
+}
+
+define i32 @zip2i32(i32 %a) nounwind {
+; RV32ZBP-LABEL: zip2i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: zip2 a0, a0
+; RV32ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 14)
+ ret i32 %tmp
+}
+
define i32 @zipi32(i32 %a) nounwind {
; RV32ZBP-LABEL: zipi32:
; RV32ZBP: # %bb.0:
@@ -101,6 +119,15 @@ define i32 @zipi32(i32 %a) nounwind {
ret i32 %tmp
}
+define i32 @zip8i32(i32 %a) nounwind {
+; RV32ZBP-LABEL: zip8i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: zip8 a0, a0
+; RV32ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 8)
+ ret i32 %tmp
+}
+
declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
define i32 @unshfl32(i32 %a, i32 %b) nounwind {
@@ -131,6 +158,24 @@ define i32 @unshfli32(i32 %a) nounwind {
ret i32 %tmp
}
+define i32 @unzip4i32(i32 %a) nounwind {
+; RV32ZBP-LABEL: unzip4i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: unzip4 a0, a0
+; RV32ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 12)
+ ret i32 %tmp
+}
+
+define i32 @unzip2i32(i32 %a) nounwind {
+; RV32ZBP-LABEL: unzip2i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: unzip2 a0, a0
+; RV32ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 14)
+ ret i32 %tmp
+}
+
define i32 @unzipi32(i32 %a) nounwind {
; RV32ZBP-LABEL: unzipi32:
; RV32ZBP: # %bb.0:
@@ -140,6 +185,15 @@ define i32 @unzipi32(i32 %a) nounwind {
ret i32 %tmp
}
+define i32 @unzip8i32(i32 %a) nounwind {
+; RV32ZBP-LABEL: unzip8i32:
+; RV32ZBP: # %bb.0:
+; RV32ZBP-NEXT: unzip8 a0, a0
+; RV32ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 8)
+ ret i32 %tmp
+}
+
declare i32 @llvm.riscv.xperm.n.i32(i32 %a, i32 %b)
define i32 @xpermn32(i32 %a, i32 %b) nounwind {
diff --git a/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
index 50b2a1b322c92..5a1736a250e57 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
@@ -100,8 +100,26 @@ define signext i32 @shfli32(i32 signext %a) nounwind {
ret i32 %tmp
}
-define signext i32 @zip_w(i32 signext %a) nounwind {
-; RV64ZBP-LABEL: zip_w:
+define signext i32 @zip4wi32(i32 signext %a) nounwind {
+; RV64ZBP-LABEL: zip4wi32:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: zip4.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 12)
+ ret i32 %tmp
+}
+
+define signext i32 @zip2wi32(i32 signext %a) nounwind {
+; RV64ZBP-LABEL: zip2wi32:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: zip2.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 14)
+ ret i32 %tmp
+}
+
+define signext i32 @zipwi32(i32 signext %a) nounwind {
+; RV64ZBP-LABEL: zipwi32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: zip.w a0, a0
; RV64ZBP-NEXT: ret
@@ -109,6 +127,15 @@ define signext i32 @zip_w(i32 signext %a) nounwind {
ret i32 %tmp
}
+define signext i32 @zip8wi32(i32 signext %a) nounwind {
+; RV64ZBP-LABEL: zip8wi32:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: zip8.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 8)
+ ret i32 %tmp
+}
+
declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
define signext i32 @unshfl32(i32 signext %a, i32 signext %b) nounwind {
@@ -141,8 +168,26 @@ define signext i32 @unshfli32(i32 signext %a) nounwind {
ret i32 %tmp
}
-define signext i32 @unzip_w(i32 signext %a) nounwind {
-; RV64ZBP-LABEL: unzip_w:
+define signext i32 @unzip4wi32(i32 signext %a) nounwind {
+; RV64ZBP-LABEL: unzip4wi32:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: unzip4.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 12)
+ ret i32 %tmp
+}
+
+define signext i32 @unzip2wi32(i32 signext %a) nounwind {
+; RV64ZBP-LABEL: unzip2wi32:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: unzip2.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 14)
+ ret i32 %tmp
+}
+
+define signext i32 @unzipwi32(i32 signext %a) nounwind {
+; RV64ZBP-LABEL: unzipwi32:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: unzip.w a0, a0
; RV64ZBP-NEXT: ret
@@ -150,6 +195,15 @@ define signext i32 @unzip_w(i32 signext %a) nounwind {
ret i32 %tmp
}
+define signext i32 @unzip8wi32(i32 signext %a) nounwind {
+; RV64ZBP-LABEL: unzip8wi32:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: unzip8.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 8)
+ ret i32 %tmp
+}
+
declare i64 @llvm.riscv.grev.i64(i64 %a, i64 %b)
define i64 @grev64(i64 %a, i64 %b) nounwind {
@@ -242,6 +296,69 @@ define i64 @shfli64(i64 %a) nounwind {
ret i64 %tmp
}
+define i64 @zip4wi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: zip4wi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: zip4.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 12)
+ ret i64 %tmp
+}
+
+define i64 @zip2wi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: zip2wi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: zip2.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 14)
+ ret i64 %tmp
+}
+
+define i64 @zipwi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: zipwi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: zip.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 15)
+ ret i64 %tmp
+}
+
+define i64 @zip8i64(i64 %a) nounwind {
+; RV64ZBP-LABEL: zip8i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: zip8 a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 24)
+ ret i64 %tmp
+}
+
+define i64 @zip4i64(i64 %a) nounwind {
+; RV64ZBP-LABEL: zip4i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: zip4 a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 28)
+ ret i64 %tmp
+}
+
+define i64 @zip2i64(i64 %a) nounwind {
+; RV64ZBP-LABEL: zip2i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: zip2 a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 30)
+ ret i64 %tmp
+}
+
+define i64 @zipi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: zipi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: zip a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.shfl.i64(i64 %a, i64 31)
+ ret i64 %tmp
+}
+
declare i64 @llvm.riscv.unshfl.i64(i64 %a, i64 %b)
define i64 @unshfl64(i64 %a, i64 %b) nounwind {
@@ -272,6 +389,69 @@ define i64 @unshfli64(i64 %a) nounwind {
ret i64 %tmp
}
+define i64 @unzip4wi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: unzip4wi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: unzip4.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 12)
+ ret i64 %tmp
+}
+
+define i64 @unzip2wi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: unzip2wi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: unzip2.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 14)
+ ret i64 %tmp
+}
+
+define i64 @unzipwi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: unzipwi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: unzip.w a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 15)
+ ret i64 %tmp
+}
+
+define i64 @unzip8i64(i64 %a) nounwind {
+; RV64ZBP-LABEL: unzip8i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: unzip8 a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 24)
+ ret i64 %tmp
+}
+
+define i64 @unzip4i64(i64 %a) nounwind {
+; RV64ZBP-LABEL: unzip4i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: unzip4 a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 28)
+ ret i64 %tmp
+}
+
+define i64 @unzip2i64(i64 %a) nounwind {
+; RV64ZBP-LABEL: unzip2i64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: unzip2 a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 30)
+ ret i64 %tmp
+}
+
+define i64 @unzipi64(i64 %a) nounwind {
+; RV64ZBP-LABEL: unzipi64:
+; RV64ZBP: # %bb.0:
+; RV64ZBP-NEXT: unzip a0, a0
+; RV64ZBP-NEXT: ret
+ %tmp = call i64 @llvm.riscv.unshfl.i64(i64 %a, i64 31)
+ ret i64 %tmp
+}
+
declare i64 @llvm.riscv.xperm.n.i64(i64 %a, i64 %b)
define i64 @xpermn64(i64 %a, i64 %b) nounwind {
More information about the llvm-commits
mailing list