[PATCH] D118020: [RISCV] Set CostPerUse for floating point registers

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead added a comment.

> Our confusion is that there are only 8 float opcodes that have compressed forms. They are all loads/stores and 4 of them are limited to RV32.
>
> I ran 453.povray from SPEC2006 on a SiFive Unmatched board with this patch applied to our downstream compiler. My result was a 1% decrease in performance.

I ran the whole SPEC2006 FP for several times and got the same performance increases(about 1% under geometric mean).
The reason why we got different results may be that there are some differences between micro-archs and downstreams(not for sure). I will run it again with pure upstream later.

> Should we look at what happens if we change the allocation order to use compressible argument registers first without changing the cost?

Yes I think it makes sense. I will have a try.
@craig.topper


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https://reviews.llvm.org/D118020