[PATCH] D120216: [DAG] try to convert multiply to shift via demanded bits

[Sanjay Patel via Phabricator via llvm-commits]

spatel marked an inline comment as done.
spatel added inline comments.


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Comment at: llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll:261
 ; PPC64LE-NEXT:    sldi 3, 3, 1
-; PPC64LE-NEXT:    add 3, 6, 3
+; PPC64LE-NEXT:    sub 3, 6, 3
 ; PPC64LE-NEXT:    add 3, 3, 4
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spatel wrote:
> xbolva00 wrote:
> > also interesting change
> Yes - this is the same test as for Mips above here.
> 
> After legalization, we have:
> 
> ```
>        t56: i64 = mul t2, Constant:i64<2>
>       t58: i64 = add t55, t56
> ...
>     t59: i64 = add t58, t57
>   t65: i64 = and t59, Constant:i64<3>
> 
> ```
> 
> So we are shifting a single meaningful demanded bit to bit 1, and I think the code is correct as shown here:
> https://alive2.llvm.org/ce/z/cqL3SC
> 
> Notice that the `sub` becomes an `add` in IR with instcombine. 
> 
> I fixed a similar gap in DAG folding with:
> a2963d871ee5
> ...but we need yet another demanded bits fold or some other sub->add fold.
> 
> I suspect it's a rare case, and it didn't seem harmful in these tests at least, so I figured it could be another follow-up if needed.
Alternatively, we could probably ignore any multiply by a power-of-2 constant in this fold since that should eventually become a `shl` by itself.


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  https://reviews.llvm.org/D120216/new/

https://reviews.llvm.org/D120216