[llvm] 7f827eb - [AArch64][RISCV][x86] add tests for mul-add demanded bits; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 20 12:20:36 PST 2022
Author: Sanjay Patel
Date: 2022-02-20T15:06:55-05:00
New Revision: 7f827ebddc38dbe7c3d7a331d3ad5a95647ff25d
URL: https://github.com/llvm/llvm-project/commit/7f827ebddc38dbe7c3d7a331d3ad5a95647ff25d
DIFF: https://github.com/llvm/llvm-project/commit/7f827ebddc38dbe7c3d7a331d3ad5a95647ff25d.diff
LOG: [AArch64][RISCV][x86] add tests for mul-add demanded bits; NFC
See #53829
Added:
llvm/test/CodeGen/X86/mul-demand.ll
Modified:
llvm/test/CodeGen/AArch64/mul_pow2.ll
llvm/test/CodeGen/RISCV/mul.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/mul_pow2.ll b/llvm/test/CodeGen/AArch64/mul_pow2.ll
index 59ac56f34aa24..31ff289b7a2f4 100644
--- a/llvm/test/CodeGen/AArch64/mul_pow2.ll
+++ b/llvm/test/CodeGen/AArch64/mul_pow2.ll
@@ -700,3 +700,48 @@ define i32 @ntest16(i32 %x) {
%mul = mul nsw i32 %x, -16
ret i32 %mul
}
+
+define i32 @muladd_demand(i32 %x, i32 %y) {
+; CHECK-LABEL: muladd_demand:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #131008
+; CHECK-NEXT: madd w8, w0, w8, w1
+; CHECK-NEXT: and w0, w8, #0x1ffc0
+; CHECK-NEXT: ret
+;
+; GISEL-LABEL: muladd_demand:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #131008
+; GISEL-NEXT: madd w8, w0, w8, w1
+; GISEL-NEXT: and w0, w8, #0x1ffc0
+; GISEL-NEXT: ret
+ %m = mul i32 %x, 131008 ; 0x0001ffc0
+ %a = add i32 %y, %m
+ %r = and i32 %a, 131008
+ ret i32 %r
+}
+
+define <4 x i32> @muladd_demand_commute(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: muladd_demand_commute:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #131008
+; CHECK-NEXT: dup v2.4s, w8
+; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s
+; CHECK-NEXT: movi v0.4s, #1, msl #16
+; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+;
+; GISEL-LABEL: muladd_demand_commute:
+; GISEL: // %bb.0:
+; GISEL-NEXT: adrp x8, .LCPI42_1
+; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI42_1]
+; GISEL-NEXT: adrp x8, .LCPI42_0
+; GISEL-NEXT: mla v1.4s, v0.4s, v2.4s
+; GISEL-NEXT: ldr q0, [x8, :lo12:.LCPI42_0]
+; GISEL-NEXT: and v0.16b, v1.16b, v0.16b
+; GISEL-NEXT: ret
+ %m = mul <4 x i32> %x, <i32 131008, i32 131008, i32 131008, i32 131008>
+ %a = add <4 x i32> %m, %y
+ %r = and <4 x i32> %a, <i32 131071, i32 131071, i32 131071, i32 131071>
+ ret <4 x i32> %r
+}
diff --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll
index 3884c67d399da..ad720808c1b5d 100644
--- a/llvm/test/CodeGen/RISCV/mul.ll
+++ b/llvm/test/CodeGen/RISCV/mul.ll
@@ -1547,3 +1547,54 @@ define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind {
ret i64 %5
}
+define i8 @muladd_demand(i8 %x, i8 %y) nounwind {
+; RV32I-LABEL: muladd_demand:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s0, a1
+; RV32I-NEXT: li a1, 14
+; RV32I-NEXT: call __mulsi3 at plt
+; RV32I-NEXT: add a0, s0, a0
+; RV32I-NEXT: andi a0, a0, 15
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: muladd_demand:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: li a2, 14
+; RV32IM-NEXT: mul a0, a0, a2
+; RV32IM-NEXT: add a0, a1, a0
+; RV32IM-NEXT: andi a0, a0, 15
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: muladd_demand:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: li a1, 14
+; RV64I-NEXT: call __muldi3 at plt
+; RV64I-NEXT: addw a0, s0, a0
+; RV64I-NEXT: andi a0, a0, 15
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: muladd_demand:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: li a2, 14
+; RV64IM-NEXT: mulw a0, a0, a2
+; RV64IM-NEXT: addw a0, a1, a0
+; RV64IM-NEXT: andi a0, a0, 15
+; RV64IM-NEXT: ret
+ %m = mul i8 %x, 14
+ %a = add i8 %y, %m
+ %r = and i8 %a, 15
+ ret i8 %r
+}
diff --git a/llvm/test/CodeGen/X86/mul-demand.ll b/llvm/test/CodeGen/X86/mul-demand.ll
new file mode 100644
index 0000000000000..0af5cb3e7a8e0
--- /dev/null
+++ b/llvm/test/CodeGen/X86/mul-demand.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
+
+define i64 @muladd_demand(i64 %x, i64 %y) {
+; CHECK-LABEL: muladd_demand:
+; CHECK: # %bb.0:
+; CHECK-NEXT: imull $131008, %edi, %eax # imm = 0x1FFC0
+; CHECK-NEXT: addl %esi, %eax
+; CHECK-NEXT: shlq $47, %rax
+; CHECK-NEXT: retq
+ %m = mul i64 %x, 131008 ; 0x0001ffc0
+ %a = add i64 %m, %y
+ %r = shl i64 %a, 47
+ ret i64 %r
+}
+
+define <2 x i64> @muladd_demand_commute(<2 x i64> %x, <2 x i64> %y) {
+; CHECK-LABEL: muladd_demand_commute:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: paddq %xmm1, %xmm0
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: retq
+ %m = mul <2 x i64> %x, <i64 131008, i64 131008>
+ %a = add <2 x i64> %y, %m
+ %r = and <2 x i64> %a, <i64 131071, i64 131071>
+ ret <2 x i64> %r
+}
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