[PATCH] D120216: [DAG] try to convert multiply to shift via demanded bits

Sanjay Patel via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Feb 20 12:02:58 PST 2022


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This is a fix for a regression discussed in:
https://github.com/llvm/llvm-project/issues/53829

We cleared more high multiplier bits with 995d400 <https://reviews.llvm.org/rG995d400f3a3c3d47bad95551dad104f686c46305>, but that can lead to worse codegen because we would fail to recognize the now disguised multiplication by neg-power-of-2 as a shift-left. The problem exists independently of the IR change in the case that the multiply already had cleared high bits. We also convert shl+sub into mul+add in instcombine's negator.

This patch fills in the high-bits to see the shift transform opportunity. Alive2 attempt to show correctness:
https://alive2.llvm.org/ce/z/GgSKVX

The AArch64, RISCV, and MIPS diffs look like clear wins. The x86 code requires an extra move register in the minimal examples, but it's still an improvement to get rid of the multiply on all CPUs that I am aware of (because multiply is never as fast as a shift).

There's a potential follow-up noted by the TODO comment. We should already convert that pattern into shl+add in IR, so it's probably not common:
https://alive2.llvm.org/ce/z/7QY_Ga


https://reviews.llvm.org/D120216

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/mul_pow2.ll
  llvm/test/CodeGen/AArch64/srem-lkk.ll
  llvm/test/CodeGen/AArch64/srem-seteq.ll
  llvm/test/CodeGen/Mips/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/PowerPC/srem-lkk.ll
  llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/mul.ll
  llvm/test/CodeGen/RISCV/srem-lkk.ll
  llvm/test/CodeGen/X86/mul-demand.ll

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