[PATCH] D120199: [X86] Use bit test instructions to optimize some logic atomic operations

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:30495
+  case AtomicRMWInst::Or:
+    SCR = 0;
+    break;
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Use enum { BIT_SET, BIT_CLEAR, BIT_RESET} to replace {0, 1, 2}?


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:30504
+  }
+  Instruction *I = AI->user_back();
+  LLVMContext &Ctx = AI->getParent()->getParent()->getContext();
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Add comments that there is only 1 user checked in shouldExpandLogicAtomicRMWInIR()?


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Comment at: llvm/lib/Target/X86/X86InstrCompiler.td:848
+               [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+multiclass ATOMIC_LOG<Format Form, string mnemonic, dag SCR> {
+  let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
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Does LOG mean logic? Rename to ATOMIC_OP?
SCR means "set, clear reset"? Maybe add comments for it, so that it is well understood.


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Comment at: llvm/lib/Target/X86/X86IntrinsicsInfo.h:40
   FIXUPIMM, FIXUPIMM_MASKZ, GATHER_AVX2,
-  ROUNDP, ROUNDS
+  ROUNDP, ROUNDS, LOCK_BITTEST
 };
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It seems LOCK_BITTEST is not used?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120199/new/

https://reviews.llvm.org/D120199