[llvm] 24bfa24 - [SelectionDAGBuilder] Simplify visitShift. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 19 12:41:10 PST 2022
Author: Craig Topper
Date: 2022-02-19T12:40:59-08:00
New Revision: 24bfa243551034bf949772146bdf27b14ce9674a
URL: https://github.com/llvm/llvm-project/commit/24bfa243551034bf949772146bdf27b14ce9674a
DIFF: https://github.com/llvm/llvm-project/commit/24bfa243551034bf949772146bdf27b14ce9674a.diff
LOG: [SelectionDAGBuilder] Simplify visitShift. NFC
This code was detecting whether the value returned by getShiftAmountTy
can represent all shift amounts. If not, it would use MVT::i32 as a
placeholder. getShiftAmountTy was updated last year to return i32
if the type returned by the target couldn't represent all values.
This means the MVT::i32 case here is dead and can the logic can
be simplified.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D120164
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 3e2dd9ec74e09..8dc6e98483aa7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -3150,26 +3150,12 @@ void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
Op1.getValueType(), DAG.getDataLayout());
- // Coerce the shift amount to the right type if we can.
+ // Coerce the shift amount to the right type if we can. This exposes the
+ // truncate or zext to optimization early.
if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
- unsigned ShiftSize = ShiftTy.getSizeInBits();
- unsigned Op2Size = Op2.getValueSizeInBits();
- SDLoc DL = getCurSDLoc();
-
- // If the operand is smaller than the shift count type, promote it.
- if (ShiftSize > Op2Size)
- Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
-
- // If the operand is larger than the shift count type but the shift
- // count type has enough bits to represent any shift value, truncate
- // it now. This is a common case and it exposes the truncate to
- // optimization early.
- else if (ShiftSize >= Log2_32_Ceil(Op1.getValueSizeInBits()))
- Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
- // Otherwise we'll need to temporarily settle for some other convenient
- // type. Type legalization will make adjustments once the shiftee is split.
- else
- Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
+ assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(Op1.getValueSizeInBits()) &&
+ "Unexpected shift type");
+ Op2 = DAG.getZExtOrTrunc(Op2, getCurSDLoc(), ShiftTy);
}
bool nuw = false;
More information about the llvm-commits
mailing list