[PATCH] D120192: [DAG] Attempt to fold bswap(shl(x,c)) -> zext(bswap(trunc(shl(x,c-bw/2))))

[Simon Pilgrim via Phabricator via llvm-commits]

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If the shl is at least half the bitwidth (i.e. the lower half of the bswap source is zero), then we can reduce the shift and perform the bswap at half the bitwidth and just zero extend.

I've currently allowed any shift value >= bw/2, but we could limit this to modulo16 so that the shl is always folded away? I'll probably enforce that limit for the InstCombine variant of this fold for PR53867, but I was wondering whether we should be more relaxed in DAG.

Based off PR51391 + PR53867


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120192

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/load-combine-big-endian.ll
  llvm/test/CodeGen/AArch64/load-combine.ll
  llvm/test/CodeGen/X86/combine-bswap.ll
  llvm/test/CodeGen/X86/load-combine.ll

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