[PATCH] D120170: [SelectionDAG] Fix off by one error in range check in DAGTypeLegalizer::ExpandShiftByConstant.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 18 18:43:09 PST 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8e7247a37797: [SelectionDAG] Fix off by one error in range check in DAGTypeLegalizer… (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D120170/new/
https://reviews.llvm.org/D120170
Files:
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -2468,7 +2468,7 @@
EVT ShTy = N->getOperand(1).getValueType();
if (N->getOpcode() == ISD::SHL) {
- if (Amt.ugt(VTBits)) {
+ if (Amt.uge(VTBits)) {
Lo = Hi = DAG.getConstant(0, DL, NVT);
} else if (Amt.ugt(NVTBits)) {
Lo = DAG.getConstant(0, DL, NVT);
@@ -2489,7 +2489,7 @@
}
if (N->getOpcode() == ISD::SRL) {
- if (Amt.ugt(VTBits)) {
+ if (Amt.uge(VTBits)) {
Lo = Hi = DAG.getConstant(0, DL, NVT);
} else if (Amt.ugt(NVTBits)) {
Lo = DAG.getNode(ISD::SRL, DL,
@@ -2510,7 +2510,7 @@
}
assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
- if (Amt.ugt(VTBits)) {
+ if (Amt.uge(VTBits)) {
Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
DAG.getConstant(NVTBits - 1, DL, ShTy));
} else if (Amt.ugt(NVTBits)) {
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