[llvm] deb73a2 - [AArch64][GlobalISel] Constrain the right MOs when lowering calls.

[Ahmed Bougacha via llvm-commits]

Author: Ahmed Bougacha
Date: 2022-02-18T13:53:13-08:00
New Revision: deb73a285b92ece59c93c2c3b4b398bdd540513c

URL: https://github.com/llvm/llvm-project/commit/deb73a285b92ece59c93c2c3b4b398bdd540513c
DIFF: https://github.com/llvm/llvm-project/commit/deb73a285b92ece59c93c2c3b4b398bdd540513c.diff

LOG: [AArch64][GlobalISel] Constrain the right MOs when lowering calls.

This was constraining the stale Info.Callee MO instead of the one we
copied into the MI.
In addition, with c8b8c8e989e, when there's an attachedcall, the
Callee is at position 1 rather than 0.

Differential Revision: https://reviews.llvm.org/D120161

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index 3027b9a36a5c3..3b4eaad4133ad 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -1059,10 +1059,10 @@ bool AArch64CallLowering::lowerTailCall(
 
   // If Callee is a reg, since it is used by a target specific instruction,
   // it must have a register class matching the constraint of that instruction.
-  if (Info.Callee.isReg())
+  if (MIB->getOperand(0).isReg())
     constrainOperandRegClass(MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
                              *MF.getSubtarget().getRegBankInfo(), *MIB,
-                             MIB->getDesc(), Info.Callee, 0);
+                             MIB->getDesc(), MIB->getOperand(0), 0);
 
   MF.getFrameInfo().setHasTailCall();
   Info.LoweredTailCall = true;
@@ -1139,12 +1139,16 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
     Opc = getCallOpcode(MF, Info.Callee.isReg(), false);
 
   auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
+  unsigned CalleeOpNo = 0;
+
   if (Opc == AArch64::BLR_RVMARKER) {
     // Add a target global address for the retainRV/claimRV runtime function
     // just before the call target.
     Function *ARCFn = *objcarc::getAttachedARCFunction(Info.CB);
     MIB.addGlobalAddress(ARCFn);
+    ++CalleeOpNo;
   }
+
   MIB.add(Info.Callee);
 
   // Tell the call which registers are clobbered.
@@ -1175,10 +1179,10 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
   // If Callee is a reg, since it is used by a target specific
   // instruction, it must have a register class matching the
   // constraint of that instruction.
-  if (Info.Callee.isReg())
+  if (MIB->getOperand(CalleeOpNo).isReg())
     constrainOperandRegClass(MF, *TRI, MRI, *Subtarget.getInstrInfo(),
                              *Subtarget.getRegBankInfo(), *MIB, MIB->getDesc(),
-                             Info.Callee, 0);
+                             MIB->getOperand(CalleeOpNo), CalleeOpNo);
 
   // Finally we can copy the returned value back into its virtual-register. In
   // symmetry with the arguments, the physical register must be an