[PATCH] D117298: [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.

Jay Foad via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Feb 18 08:11:10 PST 2022 

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf510045d820b: [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. (authored by foad).

Changed prior to commit:
  https://reviews.llvm.org/D117298?vs=399944&id=409939#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117298/new/

https://reviews.llvm.org/D117298

Files:
  llvm/test/CodeGen/AArch64/GlobalISel/swiftself.ll
  llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll
  llvm/test/CodeGen/AArch64/arm64-abi_align.ll
  llvm/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll
  llvm/test/CodeGen/AArch64/arm64-code-model-large-darwin.ll
  llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
  llvm/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll
  llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
  llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll
  llvm/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll
  llvm/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll
  llvm/test/CodeGen/AArch64/arm64-promote-const.ll
  llvm/test/CodeGen/AArch64/arm64-swizzle-tbl-i16-layout.ll
  llvm/test/CodeGen/AArch64/arm64-vector-ldst.ll
  llvm/test/CodeGen/AArch64/arm64-virtual_base.ll
  llvm/test/CodeGen/AArch64/cmpxchg-O0.ll
  llvm/test/CodeGen/AArch64/dllimport.ll
  llvm/test/CodeGen/AArch64/fast-isel-atomic.ll
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  llvm/test/CodeGen/AArch64/stack-guard-reassign.ll
  llvm/test/CodeGen/AArch64/stack-guard-sve.ll
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  llvm/test/CodeGen/AArch64/stack-tagging-unchecked-ld-st.ll
  llvm/test/CodeGen/AArch64/stack_guard_remat.ll
  llvm/test/CodeGen/AArch64/stgp.ll
  llvm/test/CodeGen/AArch64/swiftself.ll
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  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.id.ll
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  llvm/test/CodeGen/AMDGPU/commute-compares.ll
  llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
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  llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
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  llvm/test/CodeGen/AMDGPU/fdiv.f64.ll
  llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
  llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
  llvm/test/CodeGen/AMDGPU/flat-address-space.ll
  llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
  llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
  llvm/test/CodeGen/AMDGPU/fmul.f16.ll
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  llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll
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  llvm/test/CodeGen/AMDGPU/inline-asm.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
  llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
  llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.d16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
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  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
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  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
  llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
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  llvm/test/CodeGen/AMDGPU/load-local-i16.ll
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  llvm/test/CodeGen/AMDGPU/local-atomics64.ll
  llvm/test/CodeGen/AMDGPU/memcpy-scoped-aa.ll
  llvm/test/CodeGen/AMDGPU/merge-stores.ll
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  llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
  llvm/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll
  llvm/test/CodeGen/AMDGPU/operand-folding.ll
  llvm/test/CodeGen/AMDGPU/or.ll
  llvm/test/CodeGen/AMDGPU/packed-fp32.ll
  llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll
  llvm/test/CodeGen/AMDGPU/private-element-size.ll
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  llvm/test/CodeGen/AMDGPU/s_movk_i32.ll
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  llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
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  llvm/test/CodeGen/ARM/swiftself.ll
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  llvm/test/CodeGen/ARM/vector-DAGCombine.ll
  llvm/test/CodeGen/ARM/vld3.ll
  llvm/test/CodeGen/ARM/win32-ssp.ll
  llvm/test/CodeGen/Thumb/stack_guard_remat.ll
  llvm/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll
  llvm/test/CodeGen/Thumb2/stack_guard_remat.ll
  llvm/test/CodeGen/XCore/epilogue_prologue.ll
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  llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll
  llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll

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