[PATCH] D120121: [StableHashing] Hash vregs with multiple defs

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: plotfi, kyulee, lanza, paquette, manmanren, arsenm, serge-sans-paille.
Herald added a subscriber: hiraditya.
foad requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

This allows stableHashValue to be used on Machine IR that is
not in SSA form.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120121

Files:
  llvm/lib/CodeGen/MachineStableHash.cpp


Index: llvm/lib/CodeGen/MachineStableHash.cpp
===================================================================
--- llvm/lib/CodeGen/MachineStableHash.cpp
+++ llvm/lib/CodeGen/MachineStableHash.cpp
@@ -64,7 +64,10 @@
   case MachineOperand::MO_Register:
     if (Register::isVirtualRegister(MO.getReg())) {
       const MachineRegisterInfo &MRI = MO.getParent()->getMF()->getRegInfo();
-      return MRI.getVRegDef(MO.getReg())->getOpcode();
+      SmallVector<unsigned> DefOpcodes;
+      for (auto &Def : MRI.def_instructions(MO.getReg()))
+        DefOpcodes.push_back(Def.getOpcode());
+      return hash_combine_range(DefOpcodes.begin(), DefOpcodes.end());
     }
 
     // Register operands don't have target flags.


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