[llvm] acc08a2 - Add "REQUIRES: asserts" to test misched-predicate-virtreg.mir which uses "-debug-only".

[Douglas Yung via llvm-commits]

Author: Douglas Yung
Date: 2022-02-18T01:48:58-08:00
New Revision: acc08a2f1bd35a6046bffd7030bf3990ddd595c7

URL: https://github.com/llvm/llvm-project/commit/acc08a2f1bd35a6046bffd7030bf3990ddd595c7
DIFF: https://github.com/llvm/llvm-project/commit/acc08a2f1bd35a6046bffd7030bf3990ddd595c7.diff

LOG: Add "REQUIRES: asserts" to test misched-predicate-virtreg.mir which uses "-debug-only".

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir b/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
index 95e58a48b424b..dbe6aa1e6e6a6 100644
--- a/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
+++ b/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mcpu=exynos-m5 -mtriple=aarch64 -enable-misched -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o /dev/null 2>&1 | FileCheck %s
+# REQUIRES: asserts
 
 # CHECK-LABEL: ********** MI Scheduling **********
 # CHECK:       SU(0):   %0:fpr128 = COPY $q1