[PATCH] D120009: [RISCV][NFC] Add sched and adjust predicates for some instructions in Zb extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:860
 
+let Predicates = [HasStdExtZbpOrZbkb, IsRV32] in {
 // We treat zip and unzip as separate instructions, so match it directly.
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Jimerlife wrote:
> craig.topper wrote:
> > Is this not a functional change for RV64 because ZIP_RV32 will put 0b01111 in bits 24:20 which matches the 15 that was requested in the pattern?
> This change will not affect RV64. where defined ZIP_RV32 and UNZIP_RV32 also add "IsRV32" constrain.
Without this patch isel will pick these instructions on rv64. The IsRV32 on the instructions only affects the assembler or disassembler.

We need to understand what really happens on RV64 so I know if this needs to be bacported to LLVM 14


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120009/new/

https://reviews.llvm.org/D120009