[PATCH] D117654: [RISCV] Support Sinval extension and hypervisor memory management fence instructions

[eric tang via Phabricator via llvm-commits]

tangxingxin1008 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:683
+                         "sfence.vma", "$rs1, $rs2">, Sched<[]>;
+def SINVAL_VMA : RVInstR<0b0001011, 0b000, OPC_SYSTEM, (outs),
+                         (ins GPR:$rs1, GPR:$rs2),
----------------
asb wrote:
> If you defined a Priv_rr class, you could use that for sfence.vma, sinval.vma, hfence.{v,g}vma and hinval.{v,g}vma.
done.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:697
+
+def HFENCE_VVMA : RVInstR<0b0010001, 0b000, OPC_SYSTEM, (outs),
+                         (ins GPR:$rs1, GPR:$rs2),
----------------
asb wrote:
> I think these hfence instructions are technically not part of Sinval, but defined in the hypervisor extension. I understand there's a bit of a circular dependency here, so my suggestion would just be to modify the commit title to something like "Support Sinval extension and hypervisor memory management fence instructions"
done.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117654/new/

https://reviews.llvm.org/D117654