[PATCH] D120104: [AArch64] Enable fuse-literals feature by default

[Alexander Shaposhnikov via Phabricator via llvm-commits]

alexander-shaposhnikov created this revision.
alexander-shaposhnikov added reviewers: peter.smith, Wilco1.
alexander-shaposhnikov created this object with visibility "All Users".
Herald added subscribers: mstorsjo, hiraditya, kristof.beyls.
alexander-shaposhnikov requested review of this revision.
Herald added a project: LLVM.

This diff enables fuse-literals feature by default,
in particular, it adjusts instruction scheduling to place ADRP+ADD pairs together and match GCC's behavior
(see https://github.com/gcc-mirror/gcc/blob/master/gcc/config/aarch64/aarch64-fusion-pairs.def).
This also enables the linker to apply the relaxations described in 
https://github.com/ARM-software/abi-aa/commit/d2ca58c54b8e955cfef25c71822f837ae0439d73

Test plan:

1. ninja check-llvm-codegen
2. ninja check-llvm
3. ninja check-clang


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120104

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-of-shifted-dbg-value-fallback.ll
  llvm/test/CodeGen/AArch64/GlobalISel/inttoptr_add.ll
  llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll
  llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll
  llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll
  llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll
  llvm/test/CodeGen/AArch64/arm64-assert-zext-sext.ll
  llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
  llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
  llvm/test/CodeGen/AArch64/arm64-elf-constpool.ll
  llvm/test/CodeGen/AArch64/arm64-fp-imm.ll
  llvm/test/CodeGen/AArch64/arm64-tls-local-exec.ll
  llvm/test/CodeGen/AArch64/arm64_32.ll
  llvm/test/CodeGen/AArch64/fold-global-offsets.ll
  llvm/test/CodeGen/AArch64/func-argpassing.ll
  llvm/test/CodeGen/AArch64/funnel-shift.ll
  llvm/test/CodeGen/AArch64/half.ll
  llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
  llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll
  llvm/test/CodeGen/AArch64/jump-table-32.ll
  llvm/test/CodeGen/AArch64/large-consts.ll
  llvm/test/CodeGen/AArch64/machine-outliner-throw.ll
  llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
  llvm/test/CodeGen/AArch64/rotate-extract.ll
  llvm/test/CodeGen/AArch64/select_const.ll
  llvm/test/CodeGen/AArch64/select_fmf.ll
  llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll
  llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
  llvm/test/CodeGen/AArch64/srem-seteq.ll
  llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
  llvm/test/CodeGen/AArch64/sve-expand-div.ll
  llvm/test/CodeGen/AArch64/sve-fix-length-and-combine-512.ll
  llvm/test/CodeGen/AArch64/sve-vector-splat.ll
  llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-interleavedbits.ll
  llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
  llvm/test/CodeGen/AArch64/urem-lkk.ll
  llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
  llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll
  llvm/test/CodeGen/AArch64/urem-seteq.ll
  llvm/test/CodeGen/AArch64/urem-vector-lkk.ll
  llvm/test/CodeGen/AArch64/win_cst_pool.ll

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