[PATCH] D119475: [AMDGPU] Add scheduler pass to rematerialize trivial defs
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 17 12:35:28 PST 2022
rampitec added inline comments.
================
Comment at: llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir:2653
+ undef %21.sub0:vreg_128 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode
+ %21.sub1:vreg_128 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode, implicit-def $m0
+
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Do you have a similar test with sub1 and sub0 defined which would be sinkable if not subreg use?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D119475/new/
https://reviews.llvm.org/D119475
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