[llvm] bd8db27 - [AArch64] Add extra widening mul tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 17 11:11:54 PST 2022
Author: David Green
Date: 2022-02-17T19:11:45Z
New Revision: bd8db271e730f9a4f4f89176e1627b064d91e484
URL: https://github.com/llvm/llvm-project/commit/bd8db271e730f9a4f4f89176e1627b064d91e484
DIFF: https://github.com/llvm/llvm-project/commit/bd8db271e730f9a4f4f89176e1627b064d91e484.diff
LOG: [AArch64] Add extra widening mul tests. NFC
Also regenerate arm64-neon-2velem-high.ll.
Added:
llvm/test/CodeGen/AArch64/aarch64-wide-mul.ll
Modified:
llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/aarch64-wide-mul.ll b/llvm/test/CodeGen/AArch64/aarch64-wide-mul.ll
new file mode 100644
index 000000000000..b591438b7cee
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/aarch64-wide-mul.ll
@@ -0,0 +1,164 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple aarch64-unknown-linux-gnu | FileCheck %s
+
+; Tests for wider-than-legal extensions into mul/mla.
+
+define <16 x i16> @mul_i16(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: mul_i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: umull2 v2.8h, v0.16b, v1.16b
+; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b
+; CHECK-NEXT: mov v1.16b, v2.16b
+; CHECK-NEXT: ret
+entry:
+ %ea = zext <16 x i8> %a to <16 x i16>
+ %eb = zext <16 x i8> %b to <16 x i16>
+ %m = mul <16 x i16> %ea, %eb
+ ret <16 x i16> %m
+}
+
+define <16 x i32> @mul_i32(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: mul_i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-NEXT: ushll2 v4.8h, v0.16b, #0
+; CHECK-NEXT: ushll2 v5.8h, v1.16b, #0
+; CHECK-NEXT: ushll v0.8h, v1.8b, #0
+; CHECK-NEXT: umull2 v3.4s, v4.8h, v5.8h
+; CHECK-NEXT: umull2 v1.4s, v2.8h, v0.8h
+; CHECK-NEXT: umull v0.4s, v2.4h, v0.4h
+; CHECK-NEXT: umull v2.4s, v4.4h, v5.4h
+; CHECK-NEXT: ret
+entry:
+ %ea = zext <16 x i8> %a to <16 x i32>
+ %eb = zext <16 x i8> %b to <16 x i32>
+ %m = mul <16 x i32> %ea, %eb
+ ret <16 x i32> %m
+}
+
+define <16 x i64> @mul_i64(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: mul_i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ushll v2.8h, v0.8b, #0
+; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-NEXT: ushll v4.4s, v2.4h, #0
+; CHECK-NEXT: ushll v6.4s, v0.4h, #0
+; CHECK-NEXT: ushll2 v16.4s, v0.8h, #0
+; CHECK-NEXT: ushll v0.8h, v1.8b, #0
+; CHECK-NEXT: ushll2 v1.8h, v1.16b, #0
+; CHECK-NEXT: ushll2 v2.4s, v2.8h, #0
+; CHECK-NEXT: ushll v5.4s, v0.4h, #0
+; CHECK-NEXT: ushll v17.4s, v1.4h, #0
+; CHECK-NEXT: ushll2 v18.4s, v1.8h, #0
+; CHECK-NEXT: ushll2 v19.4s, v0.8h, #0
+; CHECK-NEXT: umull2 v7.2d, v16.4s, v18.4s
+; CHECK-NEXT: umull2 v3.2d, v2.4s, v19.4s
+; CHECK-NEXT: umull2 v1.2d, v4.4s, v5.4s
+; CHECK-NEXT: umull v0.2d, v4.2s, v5.2s
+; CHECK-NEXT: umull2 v5.2d, v6.4s, v17.4s
+; CHECK-NEXT: umull v2.2d, v2.2s, v19.2s
+; CHECK-NEXT: umull v4.2d, v6.2s, v17.2s
+; CHECK-NEXT: umull v6.2d, v16.2s, v18.2s
+; CHECK-NEXT: ret
+entry:
+ %ea = zext <16 x i8> %a to <16 x i64>
+ %eb = zext <16 x i8> %b to <16 x i64>
+ %m = mul <16 x i64> %ea, %eb
+ ret <16 x i64> %m
+}
+
+
+define <16 x i16> @mla_i16(<16 x i8> %a, <16 x i8> %b, <16 x i16> %c) {
+; CHECK-LABEL: mla_i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v4.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ext v5.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: umlal v2.8h, v0.8b, v1.8b
+; CHECK-NEXT: umlal v3.8h, v4.8b, v5.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: mov v1.16b, v3.16b
+; CHECK-NEXT: ret
+entry:
+ %ea = zext <16 x i8> %a to <16 x i16>
+ %eb = zext <16 x i8> %b to <16 x i16>
+ %m = mul <16 x i16> %ea, %eb
+ %d = add <16 x i16> %m, %c
+ ret <16 x i16> %d
+}
+
+define <16 x i32> @mla_i32(<16 x i8> %a, <16 x i8> %b, <16 x i32> %c) {
+; CHECK-LABEL: mla_i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ushll v6.8h, v0.8b, #0
+; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-NEXT: ushll v7.8h, v1.8b, #0
+; CHECK-NEXT: ushll2 v1.8h, v1.16b, #0
+; CHECK-NEXT: ext v16.16b, v6.16b, v6.16b, #8
+; CHECK-NEXT: ext v17.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ext v18.16b, v7.16b, v7.16b, #8
+; CHECK-NEXT: ext v19.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: umlal v4.4s, v0.4h, v1.4h
+; CHECK-NEXT: umlal v2.4s, v6.4h, v7.4h
+; CHECK-NEXT: umlal v3.4s, v16.4h, v18.4h
+; CHECK-NEXT: umlal v5.4s, v17.4h, v19.4h
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: mov v1.16b, v3.16b
+; CHECK-NEXT: mov v2.16b, v4.16b
+; CHECK-NEXT: mov v3.16b, v5.16b
+; CHECK-NEXT: ret
+entry:
+ %ea = zext <16 x i8> %a to <16 x i32>
+ %eb = zext <16 x i8> %b to <16 x i32>
+ %m = mul <16 x i32> %ea, %eb
+ %d = add <16 x i32> %m, %c
+ ret <16 x i32> %d
+}
+
+define <16 x i64> @mla_i64(<16 x i8> %a, <16 x i8> %b, <16 x i64> %c) {
+; CHECK-LABEL: mla_i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ushll v18.8h, v0.8b, #0
+; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0
+; CHECK-NEXT: ushll v25.8h, v1.8b, #0
+; CHECK-NEXT: ushll2 v1.8h, v1.16b, #0
+; CHECK-NEXT: ushll v19.4s, v18.4h, #0
+; CHECK-NEXT: ushll v20.4s, v0.4h, #0
+; CHECK-NEXT: ushll2 v18.4s, v18.8h, #0
+; CHECK-NEXT: ushll v26.4s, v25.4h, #0
+; CHECK-NEXT: ushll v27.4s, v1.4h, #0
+; CHECK-NEXT: ushll2 v25.4s, v25.8h, #0
+; CHECK-NEXT: mov v16.16b, v7.16b
+; CHECK-NEXT: mov v17.16b, v6.16b
+; CHECK-NEXT: ldp q6, q7, [sp]
+; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
+; CHECK-NEXT: ushll2 v1.4s, v1.8h, #0
+; CHECK-NEXT: ext v21.16b, v19.16b, v19.16b, #8
+; CHECK-NEXT: ext v22.16b, v20.16b, v20.16b, #8
+; CHECK-NEXT: ext v23.16b, v18.16b, v18.16b, #8
+; CHECK-NEXT: ext v28.16b, v26.16b, v26.16b, #8
+; CHECK-NEXT: ext v29.16b, v27.16b, v27.16b, #8
+; CHECK-NEXT: ext v30.16b, v25.16b, v25.16b, #8
+; CHECK-NEXT: ext v24.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ext v31.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: umlal v4.2d, v18.2s, v25.2s
+; CHECK-NEXT: umlal v17.2d, v20.2s, v27.2s
+; CHECK-NEXT: umlal v2.2d, v19.2s, v26.2s
+; CHECK-NEXT: umlal v3.2d, v21.2s, v28.2s
+; CHECK-NEXT: umlal v5.2d, v23.2s, v30.2s
+; CHECK-NEXT: umlal v16.2d, v22.2s, v29.2s
+; CHECK-NEXT: umlal v6.2d, v0.2s, v1.2s
+; CHECK-NEXT: umlal v7.2d, v24.2s, v31.2s
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: mov v1.16b, v3.16b
+; CHECK-NEXT: mov v2.16b, v4.16b
+; CHECK-NEXT: mov v3.16b, v5.16b
+; CHECK-NEXT: mov v4.16b, v17.16b
+; CHECK-NEXT: mov v5.16b, v16.16b
+; CHECK-NEXT: ret
+entry:
+ %ea = zext <16 x i8> %a to <16 x i64>
+ %eb = zext <16 x i8> %b to <16 x i64>
+ %m = mul <16 x i64> %ea, %eb
+ %d = add <16 x i64> %m, %c
+ ret <16 x i64> %d
+}
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll b/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
index 575acf723753..f1678ca19f47 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
@@ -1,11 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast \
-; RUN: < %s -verify-machineinstrs -asm-verbose=false | FileCheck %s
+; RUN: < %s -verify-machineinstrs | FileCheck %s
define <4 x i32> @test_vmull_high_n_s16(<8 x i16> %a, i16 %b) #0 {
; CHECK-LABEL: test_vmull_high_n_s16:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
-; CHECK-NEXT: smull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v1.8h, w0
+; CHECK-NEXT: smull2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %b, i32 0
@@ -18,9 +20,10 @@ entry:
define <4 x i32> @test_vmull_high_n_s16_imm(<8 x i16> %a) #0 {
; CHECK-LABEL: test_vmull_high_n_s16_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29
-; CHECK-NEXT: smull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.8h, #29
+; CHECK-NEXT: smull2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -29,9 +32,10 @@ entry:
define <2 x i64> @test_vmull_high_n_s32(<4 x i32> %a, i32 %b) #0 {
; CHECK-LABEL: test_vmull_high_n_s32:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
-; CHECK-NEXT: smull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v1.4s, w0
+; CHECK-NEXT: smull2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %b, i32 0
@@ -42,9 +46,10 @@ entry:
define <2 x i64> @test_vmull_high_n_s32_imm(<4 x i32> %a) #0 {
; CHECK-LABEL: test_vmull_high_n_s32_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #1, msl #8
-; CHECK-NEXT: smull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.4s, #1, msl #8
+; CHECK-NEXT: smull2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 511, i32 511>)
@@ -53,9 +58,10 @@ entry:
define <4 x i32> @test_vmull_high_n_u16(<8 x i16> %a, i16 %b) #0 {
; CHECK-LABEL: test_vmull_high_n_u16:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
-; CHECK-NEXT: umull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v1.8h, w0
+; CHECK-NEXT: umull2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %b, i32 0
@@ -68,9 +74,10 @@ entry:
define <4 x i32> @test_vmull_high_n_u16_imm(<8 x i16> %a) #0 {
; CHECK-LABEL: test_vmull_high_n_u16_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #17, lsl #8
-; CHECK-NEXT: umull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.8h, #17, lsl #8
+; CHECK-NEXT: umull2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vmull15.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 4352, i16 4352, i16 4352, i16 4352>)
@@ -79,9 +86,10 @@ entry:
define <2 x i64> @test_vmull_high_n_u32(<4 x i32> %a, i32 %b) #0 {
; CHECK-LABEL: test_vmull_high_n_u32:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
-; CHECK-NEXT: umull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v1.4s, w0
+; CHECK-NEXT: umull2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %b, i32 0
@@ -92,9 +100,10 @@ entry:
define <2 x i64> @test_vmull_high_n_u32_imm(<4 x i32> %a) #0 {
; CHECK-LABEL: test_vmull_high_n_u32_imm:
-; CHECK-NEXT: mvni [[REPLICATE:v[0-9]+]].4s, #1, msl #8
-; CHECK-NEXT: umull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mvni v1.4s, #1, msl #8
+; CHECK-NEXT: umull2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vmull9.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 4294966784, i32 4294966784>)
@@ -103,9 +112,10 @@ entry:
define <4 x i32> @test_vqdmull_high_n_s16(<8 x i16> %a, i16 %b) #0 {
; CHECK-LABEL: test_vqdmull_high_n_s16:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
-; CHECK-NEXT: sqdmull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v1.8h, w0
+; CHECK-NEXT: sqdmull2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %b, i32 0
@@ -118,9 +128,10 @@ entry:
define <4 x i32> @test_vqdmull_high_n_s16_imm(<8 x i16> %a) #0 {
; CHECK-LABEL: test_vqdmull_high_n_s16_imm:
-; CHECK-NEXT: mvni [[REPLICATE:v[0-9]+]].8h, #17, lsl #8
-; CHECK-NEXT: sqdmull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mvni v1.8h, #17, lsl #8
+; CHECK-NEXT: sqdmull2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vqdmull15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 61183, i16 61183, i16 61183, i16 61183>)
@@ -129,9 +140,10 @@ entry:
define <2 x i64> @test_vqdmull_high_n_s32(<4 x i32> %a, i32 %b) #0 {
; CHECK-LABEL: test_vqdmull_high_n_s32:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
-; CHECK-NEXT: sqdmull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v1.4s, w0
+; CHECK-NEXT: sqdmull2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %b, i32 0
@@ -142,9 +154,10 @@ entry:
define <2 x i64> @test_vqdmull_high_n_s32_imm(<4 x i32> %a) #0 {
; CHECK-LABEL: test_vqdmull_high_n_s32_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29
-; CHECK-NEXT: sqdmull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.4s, #29
+; CHECK-NEXT: sqdmull2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vqdmull9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
@@ -153,9 +166,10 @@ entry:
define <4 x i32> @test_vmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
; CHECK-LABEL: test_vmlal_high_n_s16:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
-; CHECK-NEXT: smlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v2.8h, w0
+; CHECK-NEXT: smlal2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
@@ -169,9 +183,10 @@ entry:
define <4 x i32> @test_vmlal_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-LABEL: test_vmlal_high_n_s16_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29
-; CHECK-NEXT: smlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.8h, #29
+; CHECK-NEXT: smlal2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -181,9 +196,10 @@ entry:
define <2 x i64> @test_vmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
; CHECK-LABEL: test_vmlal_high_n_s32:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
-; CHECK-NEXT: smlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v2.4s, w0
+; CHECK-NEXT: smlal2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -195,9 +211,10 @@ entry:
define <2 x i64> @test_vmlal_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
; CHECK-LABEL: test_vmlal_high_n_s32_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29
-; CHECK-NEXT: smlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #29
+; CHECK-NEXT: smlal2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
@@ -207,9 +224,10 @@ entry:
define <4 x i32> @test_vmlal_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
; CHECK-LABEL: test_vmlal_high_n_u16:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
-; CHECK-NEXT: umlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v2.8h, w0
+; CHECK-NEXT: umlal2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
@@ -223,9 +241,10 @@ entry:
define <4 x i32> @test_vmlal_high_n_u16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-LABEL: test_vmlal_high_n_u16_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29
-; CHECK-NEXT: umlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.8h, #29
+; CHECK-NEXT: umlal2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -235,9 +254,10 @@ entry:
define <2 x i64> @test_vmlal_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
; CHECK-LABEL: test_vmlal_high_n_u32:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
-; CHECK-NEXT: umlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v2.4s, w0
+; CHECK-NEXT: umlal2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -249,9 +269,10 @@ entry:
define <2 x i64> @test_vmlal_high_n_u32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
; CHECK-LABEL: test_vmlal_high_n_u32_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29
-; CHECK-NEXT: umlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #29
+; CHECK-NEXT: umlal2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
@@ -261,9 +282,10 @@ entry:
define <4 x i32> @test_vqdmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
; CHECK-LABEL: test_vqdmlal_high_n_s16:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
-; CHECK-NEXT: sqdmlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v2.8h, w0
+; CHECK-NEXT: sqdmlal2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
@@ -277,9 +299,10 @@ entry:
define <4 x i32> @test_vqdmlal_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-LABEL: test_vqdmlal_high_n_s16_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29
-; CHECK-NEXT: sqdmlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.8h, #29
+; CHECK-NEXT: sqdmlal2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vqdmlal15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -289,9 +312,10 @@ entry:
define <2 x i64> @test_vqdmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
; CHECK-LABEL: test_vqdmlal_high_n_s32:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
-; CHECK-NEXT: sqdmlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v2.4s, w0
+; CHECK-NEXT: sqdmlal2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -303,9 +327,10 @@ entry:
define <2 x i64> @test_vqdmlal_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
; CHECK-LABEL: test_vqdmlal_high_n_s32_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29
-; CHECK-NEXT: sqdmlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #29
+; CHECK-NEXT: sqdmlal2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vqdmlal9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
@@ -315,9 +340,10 @@ entry:
define <4 x i32> @test_vmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
; CHECK-LABEL: test_vmlsl_high_n_s16:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
-; CHECK-NEXT: smlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v2.8h, w0
+; CHECK-NEXT: smlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
@@ -331,9 +357,10 @@ entry:
define <4 x i32> @test_vmlsl_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-LABEL: test_vmlsl_high_n_s16_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29
-; CHECK-NEXT: smlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.8h, #29
+; CHECK-NEXT: smlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -343,9 +370,10 @@ entry:
define <2 x i64> @test_vmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
; CHECK-LABEL: test_vmlsl_high_n_s32:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
-; CHECK-NEXT: smlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v2.4s, w0
+; CHECK-NEXT: smlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -357,9 +385,10 @@ entry:
define <2 x i64> @test_vmlsl_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
; CHECK-LABEL: test_vmlsl_high_n_s32_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29
-; CHECK-NEXT: smlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #29
+; CHECK-NEXT: smlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
@@ -369,9 +398,10 @@ entry:
define <4 x i32> @test_vmlsl_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
; CHECK-LABEL: test_vmlsl_high_n_u16:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
-; CHECK-NEXT: umlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v2.8h, w0
+; CHECK-NEXT: umlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
@@ -385,9 +415,10 @@ entry:
define <4 x i32> @test_vmlsl_high_n_u16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-LABEL: test_vmlsl_high_n_u16_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29
-; CHECK-NEXT: umlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.8h, #29
+; CHECK-NEXT: umlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vmull2.i.i.i = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -397,9 +428,10 @@ entry:
define <2 x i64> @test_vmlsl_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
; CHECK-LABEL: test_vmlsl_high_n_u32:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
-; CHECK-NEXT: umlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v2.4s, w0
+; CHECK-NEXT: umlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -411,9 +443,10 @@ entry:
define <2 x i64> @test_vmlsl_high_n_u32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
; CHECK-LABEL: test_vmlsl_high_n_u32_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29
-; CHECK-NEXT: umlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #29
+; CHECK-NEXT: umlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vmull2.i.i.i = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
@@ -423,9 +456,10 @@ entry:
define <4 x i32> @test_vqdmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
; CHECK-LABEL: test_vqdmlsl_high_n_s16:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].8h, w0
-; CHECK-NEXT: sqdmlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v2.8h, w0
+; CHECK-NEXT: sqdmlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
@@ -439,9 +473,10 @@ entry:
define <4 x i32> @test_vqdmlsl_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-LABEL: test_vqdmlsl_high_n_s16_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29
-; CHECK-NEXT: sqdmlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.8h, #29
+; CHECK-NEXT: sqdmlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%vqdmlsl15.i.i = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> <i16 29, i16 29, i16 29, i16 29>)
@@ -451,9 +486,10 @@ entry:
define <2 x i64> @test_vqdmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
; CHECK-LABEL: test_vqdmlsl_high_n_s32:
-; CHECK-NEXT: dup [[REPLICATE:v[0-9]+]].4s, w0
-; CHECK-NEXT: sqdmlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v2.4s, w0
+; CHECK-NEXT: sqdmlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -465,9 +501,10 @@ entry:
define <2 x i64> @test_vqdmlsl_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
; CHECK-LABEL: test_vqdmlsl_high_n_s32_imm:
-; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29
-; CHECK-NEXT: sqdmlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.4s, #29
+; CHECK-NEXT: sqdmlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
%vqdmlsl9.i.i = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> <i32 29, i32 29>)
@@ -477,8 +514,10 @@ entry:
define <2 x float> @test_vmul_n_f32(<2 x float> %a, float %b) #0 {
; CHECK-LABEL: test_vmul_n_f32:
-; CHECK-NEXT: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: fmul v0.2s, v0.2s, v1.s[0]
+; CHECK-NEXT: ret
entry:
%vecinit.i = insertelement <2 x float> undef, float %b, i32 0
%vecinit1.i = insertelement <2 x float> %vecinit.i, float %b, i32 1
@@ -488,8 +527,10 @@ entry:
define <4 x float> @test_vmulq_n_f32(<4 x float> %a, float %b) #0 {
; CHECK-LABEL: test_vmulq_n_f32:
-; CHECK-NEXT: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: fmul v0.4s, v0.4s, v1.s[0]
+; CHECK-NEXT: ret
entry:
%vecinit.i = insertelement <4 x float> undef, float %b, i32 0
%vecinit1.i = insertelement <4 x float> %vecinit.i, float %b, i32 1
@@ -501,8 +542,10 @@ entry:
define <2 x double> @test_vmulq_n_f64(<2 x double> %a, double %b) #0 {
; CHECK-LABEL: test_vmulq_n_f64:
-; CHECK-NEXT: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: fmul v0.2d, v0.2d, v1.d[0]
+; CHECK-NEXT: ret
entry:
%vecinit.i = insertelement <2 x double> undef, double %b, i32 0
%vecinit1.i = insertelement <2 x double> %vecinit.i, double %b, i32 1
@@ -512,8 +555,10 @@ entry:
define <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x float> %b, float %n) #0 {
; CHECK-LABEL: test_vfma_n_f32:
-; CHECK-NEXT: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[{{[0-9]+}}]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT: fmla v0.2s, v1.2s, v2.s[0]
+; CHECK-NEXT: ret
entry:
%vecinit.i = insertelement <2 x float> undef, float %n, i32 0
%vecinit1.i = insertelement <2 x float> %vecinit.i, float %n, i32 1
@@ -523,8 +568,10 @@ entry:
define <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x float> %b, float %n) #0 {
; CHECK-LABEL: test_vfmaq_n_f32:
-; CHECK-NEXT: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[{{[0-9]+}}]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT: fmla v0.4s, v1.4s, v2.s[0]
+; CHECK-NEXT: ret
entry:
%vecinit.i = insertelement <4 x float> undef, float %n, i32 0
%vecinit1.i = insertelement <4 x float> %vecinit.i, float %n, i32 1
@@ -536,8 +583,10 @@ entry:
define <2 x float> @test_vfms_n_f32(<2 x float> %a, <2 x float> %b, float %n) #0 {
; CHECK-LABEL: test_vfms_n_f32:
-; CHECK-NEXT: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[{{[0-9]+}}]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT: fmls v0.2s, v1.2s, v2.s[0]
+; CHECK-NEXT: ret
entry:
%vecinit.i = insertelement <2 x float> undef, float %n, i32 0
%vecinit1.i = insertelement <2 x float> %vecinit.i, float %n, i32 1
@@ -548,8 +597,10 @@ entry:
define <4 x float> @test_vfmsq_n_f32(<4 x float> %a, <4 x float> %b, float %n) #0 {
; CHECK-LABEL: test_vfmsq_n_f32:
-; CHECK-NEXT: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[{{[0-9]+}}]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT: fmls v0.4s, v1.4s, v2.s[0]
+; CHECK-NEXT: ret
entry:
%vecinit.i = insertelement <4 x float> undef, float %n, i32 0
%vecinit1.i = insertelement <4 x float> %vecinit.i, float %n, i32 1
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