[PATCH] D117003: [SchedModels][CortexA55] Add ASIMD integer instructioins

[Pavel Kosov via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG37fa99eda0f5: [SchedModels][CortexA55] Add ASIMD integer instructions (authored by kpdev42).

Changed prior to commit:
  https://reviews.llvm.org/D117003?vs=407874&id=409560#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117003/new/

https://reviews.llvm.org/D117003

Files:
  llvm/lib/Target/AArch64/AArch64SchedA55.td
  llvm/test/Analysis/CostModel/AArch64/vector-select.ll
  llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
  llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
  llvm/test/CodeGen/AArch64/active_lane_mask.ll
  llvm/test/CodeGen/AArch64/addsub-constant-folding.ll
  llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
  llvm/test/CodeGen/AArch64/arm64-fcopysign.ll
  llvm/test/CodeGen/AArch64/arm64-sli-sri-opt.ll
  llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
  llvm/test/CodeGen/AArch64/arm64-vhadd.ll
  llvm/test/CodeGen/AArch64/cmp-select-sign.ll
  llvm/test/CodeGen/AArch64/dag-numsignbits.ll
  llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-signed.ll
  llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll
  llvm/test/CodeGen/AArch64/expand-vector-rot.ll
  llvm/test/CodeGen/AArch64/f16-instructions.ll
  llvm/test/CodeGen/AArch64/fcopysign.ll
  llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
  llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
  llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
  llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
  llvm/test/CodeGen/AArch64/minmax-of-minmax.ll
  llvm/test/CodeGen/AArch64/minmax.ll
  llvm/test/CodeGen/AArch64/overeager_mla_fusing.ll
  llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/sat-add.ll
  llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
  llvm/test/CodeGen/AArch64/signbit-shift.ll
  llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
  llvm/test/CodeGen/AArch64/sinksplat.ll
  llvm/test/CodeGen/AArch64/sitofp-fixed-legal.ll
  llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
  llvm/test/CodeGen/AArch64/sve-vscale-attr.ll
  llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
  llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
  llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll
  llvm/test/CodeGen/AArch64/usub_sat_vec.ll
  llvm/test/CodeGen/AArch64/vec_cttz.ll
  llvm/test/CodeGen/AArch64/vec_uaddo.ll
  llvm/test/CodeGen/AArch64/vec_umulo.ll
  llvm/test/CodeGen/AArch64/vecreduce-add.ll
  llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
  llvm/test/CodeGen/AArch64/vector-fcopysign.ll
  llvm/test/CodeGen/AArch64/vselect-constants.ll
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-neon-instructions.s

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