[llvm] 0b93e90 - Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove"

[Ben Shi via llvm-commits]

Author: Ben Shi
Date: 2022-02-17T17:27:37+08:00
New Revision: 0b93e90971c0a43199e2da70c9422ebb073080ae

URL: https://github.com/llvm/llvm-project/commit/0b93e90971c0a43199e2da70c9422ebb073080ae
DIFF: https://github.com/llvm/llvm-project/commit/0b93e90971c0a43199e2da70c9422ebb073080ae.diff

LOG: Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove"

This reverts commit 23a50736004e94704a2393aa36a905d737f2b20f.

Although this patch achieved better codegen in most cases, it is really
important to accurately describe the cost of instructions. So I revert it.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    llvm/test/CodeGen/RISCV/unroll-loop-cse.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index a5f072c7c2601..8f931c6ad1d9d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -998,8 +998,6 @@ bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
     return (MI.getOperand(1).isReg() &&
             MI.getOperand(1).getReg() == RISCV::X0) ||
            (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0);
-  case RISCV::LUI:
-    return MI.getOperand(1).getTargetFlags() != RISCVII::MO_HI;
   }
   return MI.isAsCheapAsAMove();
 }

diff  --git a/llvm/test/CodeGen/RISCV/unroll-loop-cse.ll b/llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
index 91aec53c47210..00b0d32e07d30 100644
--- a/llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
+++ b/llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
@@ -18,20 +18,28 @@ define signext i32 @unroll_loop_cse() {
 ; CHECK-NEXT:    bne a3, a4, .LBB0_6
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    addi a1, a1, %lo(x)
-; CHECK-NEXT:    lw a3, 4(a1)
+; CHECK-NEXT:    lw a1, 4(a1)
 ; CHECK-NEXT:    addi a2, a2, %lo(check)
-; CHECK-NEXT:    lw a4, 4(a2)
-; CHECK-NEXT:    bne a3, a4, .LBB0_6
+; CHECK-NEXT:    lw a2, 4(a2)
+; CHECK-NEXT:    bne a1, a2, .LBB0_6
 ; CHECK-NEXT:  # %bb.2:
+; CHECK-NEXT:    lui a1, %hi(x)
+; CHECK-NEXT:    addi a1, a1, %lo(x)
 ; CHECK-NEXT:    lw a3, 8(a1)
+; CHECK-NEXT:    lui a2, %hi(check)
+; CHECK-NEXT:    addi a2, a2, %lo(check)
 ; CHECK-NEXT:    lw a4, 8(a2)
 ; CHECK-NEXT:    bne a3, a4, .LBB0_6
 ; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    lw a3, 12(a1)
-; CHECK-NEXT:    lw a4, 12(a2)
-; CHECK-NEXT:    bne a3, a4, .LBB0_6
+; CHECK-NEXT:    lw a1, 12(a1)
+; CHECK-NEXT:    lw a2, 12(a2)
+; CHECK-NEXT:    bne a1, a2, .LBB0_6
 ; CHECK-NEXT:  # %bb.4:
+; CHECK-NEXT:    lui a1, %hi(x)
+; CHECK-NEXT:    addi a1, a1, %lo(x)
 ; CHECK-NEXT:    lw a3, 16(a1)
+; CHECK-NEXT:    lui a2, %hi(check)
+; CHECK-NEXT:    addi a2, a2, %lo(check)
 ; CHECK-NEXT:    lw a4, 16(a2)
 ; CHECK-NEXT:    bne a3, a4, .LBB0_6
 ; CHECK-NEXT:  # %bb.5: