[llvm] 8595677 - [IndVars] Don't run full optimization pipeline in test (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 17 00:29:46 PST 2022
Author: Nikita Popov
Date: 2022-02-17T09:28:33+01:00
New Revision: 859567725d8971477ed6a14799645c818c7878ad
URL: https://github.com/llvm/llvm-project/commit/859567725d8971477ed6a14799645c818c7878ad
DIFF: https://github.com/llvm/llvm-project/commit/859567725d8971477ed6a14799645c818c7878ad.diff
LOG: [IndVars] Don't run full optimization pipeline in test (NFC)
This extracts the IR prior to IndVarSimplify and only runs the
single pass.
Added:
Modified:
llvm/test/Transforms/IndVarSimplify/X86/pr45360.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/IndVarSimplify/X86/pr45360.ll b/llvm/test/Transforms/IndVarSimplify/X86/pr45360.ll
index 8f43029fa3034..a124dbd970d69 100644
--- a/llvm/test/Transforms/IndVarSimplify/X86/pr45360.ll
+++ b/llvm/test/Transforms/IndVarSimplify/X86/pr45360.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; TODO: Run under new PM after switch. The IR is the same but basic block labels are
diff erent.
-; RUN: opt -S -O2 -scev-cheap-expansion-budget=1024 %s -enable-new-pm=0 | FileCheck %s
+; RUN: opt -S -indvars -scev-cheap-expansion-budget=1024 %s | FileCheck %s
; See https://bugs.llvm.org/show_bug.cgi?id=45360
; This is reduced from that (runnable) test.
@@ -17,123 +16,97 @@ target triple = "x86_64-pc-linux-gnu"
@b = dso_local global i32 0, align 4
@e = dso_local global i32 0, align 4
-define dso_local i32 @main() {
+define i32 @main() {
; CHECK-LABEL: @main(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[I6:%.*]] = load i32, i32* @a, align 4
; CHECK-NEXT: [[I24:%.*]] = load i32, i32* @b, align 4
-; CHECK-NEXT: [[D_PROMOTED7:%.*]] = load i32, i32* @d, align 4
-; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[D_PROMOTED7]], [[I6]]
-; CHECK-NEXT: [[I21:%.*]] = icmp eq i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[I21]], label [[BB27_THREAD:%.*]], label [[BB27_PREHEADER:%.*]]
-; CHECK: bb27.preheader:
-; CHECK-NEXT: [[I26:%.*]] = urem i32 [[I24]], [[TMP0]]
-; CHECK-NEXT: store i32 [[I26]], i32* @e, align 4
-; CHECK-NEXT: [[I30_NOT:%.*]] = icmp eq i32 [[I26]], 0
-; CHECK-NEXT: br label [[BB27:%.*]]
+; CHECK-NEXT: [[D_PROMOTED10:%.*]] = load i32, i32* @d, align 4
+; CHECK-NEXT: br label [[BB1:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: br label [[BB5:%.*]]
+; CHECK: bb13.preheader:
+; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i32 [ [[TMP0:%.*]], [[BB5]] ]
+; CHECK-NEXT: [[I21:%.*]] = icmp eq i32 [[DOTLCSSA]], 0
+; CHECK-NEXT: br i1 [[I21]], label [[BB27_THREAD:%.*]], label [[BB27:%.*]]
+; CHECK: bb5:
+; CHECK-NEXT: [[TMP0]] = and i32 [[D_PROMOTED10]], [[I6]]
+; CHECK-NEXT: br i1 false, label [[BB5]], label [[BB13_PREHEADER:%.*]]
; CHECK: bb27.thread:
-; CHECK-NEXT: store i32 0, i32* @d, align 4
-; CHECK-NEXT: store i32 -1, i32* @f, align 4
+; CHECK-NEXT: [[DOTLCSSA_LCSSA:%.*]] = phi i32 [ [[DOTLCSSA]], [[BB13_PREHEADER]] ]
+; CHECK-NEXT: [[I11_LCSSA_LCSSA:%.*]] = phi i32 [ -1, [[BB13_PREHEADER]] ]
+; CHECK-NEXT: store i32 [[DOTLCSSA_LCSSA]], i32* @d, align 4
+; CHECK-NEXT: store i32 [[I11_LCSSA_LCSSA]], i32* @f, align 4
; CHECK-NEXT: store i32 0, i32* @c, align 4
+; CHECK-NEXT: store i32 0, i32* @e, align 4
; CHECK-NEXT: br label [[BB32:%.*]]
; CHECK: bb27:
+; CHECK-NEXT: [[I26:%.*]] = urem i32 [[I24]], [[DOTLCSSA]]
+; CHECK-NEXT: store i32 [[I26]], i32* @e, align 4
+; CHECK-NEXT: [[I30_NOT:%.*]] = icmp eq i32 [[I26]], 0
; CHECK-NEXT: br i1 [[I30_NOT]], label [[BB32_LOOPEXIT:%.*]], label [[BB36:%.*]]
; CHECK: bb32.loopexit:
-; CHECK-NEXT: store i32 [[TMP0]], i32* @d, align 4
-; CHECK-NEXT: store i32 -1, i32* @f, align 4
+; CHECK-NEXT: [[DOTLCSSA_LCSSA15:%.*]] = phi i32 [ [[DOTLCSSA]], [[BB27]] ]
+; CHECK-NEXT: [[I11_LCSSA_LCSSA14:%.*]] = phi i32 [ -1, [[BB27]] ]
+; CHECK-NEXT: store i32 [[DOTLCSSA_LCSSA15]], i32* @d, align 4
+; CHECK-NEXT: store i32 [[I11_LCSSA_LCSSA14]], i32* @f, align 4
+; CHECK-NEXT: store i32 0, i32* @c, align 4
; CHECK-NEXT: br label [[BB32]]
; CHECK: bb32:
-; CHECK-NEXT: [[C_SINK:%.*]] = phi i32* [ @c, [[BB32_LOOPEXIT]] ], [ @e, [[BB27_THREAD]] ]
-; CHECK-NEXT: store i32 0, i32* [[C_SINK]], align 4
; CHECK-NEXT: ret i32 0
; CHECK: bb36:
; CHECK-NEXT: store i32 1, i32* @c, align 4
-; CHECK-NEXT: br i1 [[I21]], label [[BB27_THREAD]], label [[BB27]]
+; CHECK-NEXT: br label [[BB1]]
;
bb:
- %i = alloca i32, align 4
- store i32 0, i32* %i, align 4
- br label %bb1
-
-bb1:
- store i32 0, i32* @f, align 4
- br label %bb2
-
-bb2:
- %i3 = load i32, i32* @f, align 4
- %i4 = icmp sge i32 %i3, 0
- br i1 %i4, label %bb5, label %bb12
-
-bb5:
%i6 = load i32, i32* @a, align 4
- %i7 = load i32, i32* @d, align 4
- %i8 = and i32 %i7, %i6
- store i32 %i8, i32* @d, align 4
- br label %bb9
-
-bb9:
- %i10 = load i32, i32* @f, align 4
- %i11 = add nsw i32 %i10, -1
- store i32 %i11, i32* @f, align 4
- br label %bb2
-
-bb12:
- store i32 0, i32* @c, align 4
- br label %bb13
-
-bb13:
- %i14 = load i32, i32* @c, align 4
- %i15 = icmp sle i32 %i14, 0
- br i1 %i15, label %bb16, label %bb39
-
-bb16:
- %i17 = load i32, i32* @f, align 4
- %i18 = icmp ne i32 %i17, 0
- br i1 %i18, label %bb19, label %bb34
-
-bb19:
- %i20 = load i32, i32* @d, align 4
- %i21 = icmp eq i32 %i20, 0
- br i1 %i21, label %bb22, label %bb23
-
-bb22:
- br label %bb27
-
-bb23:
%i24 = load i32, i32* @b, align 4
- %i25 = load i32, i32* @d, align 4
- %i26 = urem i32 %i24, %i25
- br label %bb27
-
-bb27:
- %i28 = phi i32 [ 0, %bb22 ], [ %i26, %bb23 ]
- store i32 %i28, i32* @e, align 4
- %i29 = load i32, i32* @e, align 4
- %i30 = icmp ne i32 %i29, 0
- br i1 %i30, label %bb31, label %bb32
+ %d.promoted10 = load i32, i32* @d, align 4
+ br label %bb1
-bb31:
- br label %bb33
+bb1: ; preds = %bb36, %bb
+ br label %bb5
+
+bb13.preheader: ; preds = %bb5
+ %.lcssa = phi i32 [ %0, %bb5 ]
+ %i11.lcssa = phi i32 [ %i11, %bb5 ]
+ %i21 = icmp eq i32 %.lcssa, 0
+ br i1 %i21, label %bb27.thread, label %bb27
+
+bb5: ; preds = %bb1, %bb5
+ %storemerge6 = phi i32 [ 0, %bb1 ], [ %i11, %bb5 ]
+ %0 = and i32 %d.promoted10, %i6
+ %i11 = add nsw i32 %storemerge6, -1
+ %i4 = icmp sgt i32 %storemerge6, 0
+ br i1 %i4, label %bb5, label %bb13.preheader
+
+bb27.thread: ; preds = %bb13.preheader
+ %.lcssa.lcssa = phi i32 [ %.lcssa, %bb13.preheader ]
+ %i11.lcssa.lcssa = phi i32 [ %i11.lcssa, %bb13.preheader ]
+ store i32 %.lcssa.lcssa, i32* @d, align 4
+ store i32 %i11.lcssa.lcssa, i32* @f, align 4
+ store i32 0, i32* @c, align 4
+ store i32 0, i32* @e, align 4
+ br label %bb32
+
+bb27: ; preds = %bb13.preheader
+ %i26 = urem i32 %i24, %.lcssa
+ store i32 %i26, i32* @e, align 4
+ %i30.not = icmp eq i32 %i26, 0
+ br i1 %i30.not, label %bb32.loopexit, label %bb36
+
+bb32.loopexit: ; preds = %bb27
+ %.lcssa.lcssa15 = phi i32 [ %.lcssa, %bb27 ]
+ %i11.lcssa.lcssa14 = phi i32 [ %i11.lcssa, %bb27 ]
+ store i32 %.lcssa.lcssa15, i32* @d, align 4
+ store i32 %i11.lcssa.lcssa14, i32* @f, align 4
+ store i32 0, i32* @c, align 4
+ br label %bb32
-bb32:
+bb32: ; preds = %bb32.loopexit, %bb27.thread
ret i32 0
-bb33:
- br label %bb35
-
-bb34:
- store i32 0, i32* @d, align 4
- br label %bb35
-
-bb35:
- br label %bb36
-
-bb36:
- %i37 = load i32, i32* @c, align 4
- %i38 = add nsw i32 %i37, 1
- store i32 %i38, i32* @c, align 4
- br label %bb13
-
-bb39:
+bb36: ; preds = %bb27
+ store i32 1, i32* @c, align 4
br label %bb1
}
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