[PATCH] D119934: [RISCV] Fix a mistake in PostprocessISelDAG

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll:183
+; RV32I-NEXT:    sw a3, %lo(g_8)(a0)
+; RV32I-NEXT:    sw a1, %lo(g_8+4)(a0)
+; RV32I-NEXT:    ret
----------------
This was already generated. If you use i32 loads/stores with @g_4 then both RV32 and RV64 see codegen differences. Using an i64 on RV32 gets a TokenFactor to glue together the splitting of the illegal i64 store into two legal i32 stores and so gives you a root node that's not one of the nodes you want to optimise.


================
Comment at: llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll:194-195
+; RV64I-NEXT:    ld a1, %lo(g_8)(a0)
+; RV64I-NEXT:    addi a1, a1, 1
+; RV64I-NEXT:    sd a1, %lo(g_8)(a0)
+; RV64I-NEXT:    ret
----------------
Without this patch these two lines were:
```
        addi    a0, a0, %lo(g_8)
        addi    a1, a1, 1
        sd      a1, 0(a0)
```
i.e. the %lo wasn't folded into the store's immediate due to the store being the root node


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119934/new/

https://reviews.llvm.org/D119934