[PATCH] D119934: [RISCV] Fix a mistake in PostprocessISelDAG

[Haocong Lu via Phabricator via llvm-commits]

Luhaocong updated this revision to Diff 409461.
Luhaocong retitled this revision from "[RISCV][NFC] Fix a mistake in PostprocessISelDAG" to "[RISCV] Fix a mistake in PostprocessISelDAG".
Luhaocong added a comment.

upload a test case


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119934/new/

https://reviews.llvm.org/D119934

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll


Index: llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
===================================================================
--- llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
+++ llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
@@ -166,6 +166,48 @@
    ret void
 }
 
+define dso_local void @inc_g_8(i32 signext %a) nounwind {
+; RV32I-LABEL: inc_g_8:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    beqz a0, .LBB8_2
+; RV32I-NEXT:  # %bb.1: # %if.end
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB8_2: # %if.then
+; RV32I-NEXT:    lui a0, %hi(g_8)
+; RV32I-NEXT:    lw a1, %lo(g_8)(a0)
+; RV32I-NEXT:    lw a2, %lo(g_8+4)(a0)
+; RV32I-NEXT:    addi a3, a1, 1
+; RV32I-NEXT:    sltu a1, a3, a1
+; RV32I-NEXT:    add a1, a2, a1
+; RV32I-NEXT:    sw a3, %lo(g_8)(a0)
+; RV32I-NEXT:    sw a1, %lo(g_8+4)(a0)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: inc_g_8:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    beqz a0, .LBB8_2
+; RV64I-NEXT:  # %bb.1: # %if.end
+; RV64I-NEXT:    ret
+; RV64I-NEXT:  .LBB8_2: # %if.then
+; RV64I-NEXT:    lui a0, %hi(g_8)
+; RV64I-NEXT:    ld a1, %lo(g_8)(a0)
+; RV64I-NEXT:    addi a1, a1, 1
+; RV64I-NEXT:    sd a1, %lo(g_8)(a0)
+; RV64I-NEXT:    ret
+entry:
+  %cmp = icmp eq i32 %a, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  %0 = load i64, i64* @g_8
+  %inc = add i64 %0, 1
+  store i64 %inc, i64* @g_8
+  br label %if.end
+
+if.end:
+  ret void
+}
+
 ; Check for folds in accesses to the second element of an i64 array.
 
 @ga_8 = dso_local local_unnamed_addr global [2 x i64] zeroinitializer, align 8
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -130,6 +130,7 @@
 }
 
 void RISCVDAGToDAGISel::PostprocessISelDAG() {
+  HandleSDNode Dummy(CurDAG->getRoot());
   SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
 
   bool MadeChange = false;
@@ -144,6 +145,8 @@
     MadeChange |= doPeepholeMaskedRVV(N);
   }
 
+  CurDAG->setRoot(Dummy.getValue());
+
   if (MadeChange)
     CurDAG->RemoveDeadNodes();
 }


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