[PATCH] D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3529
+  ///    amount of bits in these two shifts is summed up to OpSizeInBits.
+  bool matchShifts(SDValue &Op, const APInt &C, bool IsLeft) {
+    ShiftInfo &Info = UnmatchedShifts[Op];
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don't pass SDValue by reference - its just a pointer + int - it should pass by value very cheaply


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3585
+public:
+  SDValue simplify(const SDValue &Value, SelectionDAG &DAG, const SDLoc &DL) {
+    assert(Result.size() == 0 && UnmatchedShifts.size() == 0 &&
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don't pass SDValue by reference


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111530/new/

https://reviews.llvm.org/D111530