[llvm] cfbbcc5 - [RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 16 09:22:26 PST 2022
Author: Craig Topper
Date: 2022-02-16T09:22:11-08:00
New Revision: cfbbcc544c39b008bce5612148797d0f63bd26c7
URL: https://github.com/llvm/llvm-project/commit/cfbbcc544c39b008bce5612148797d0f63bd26c7
DIFF: https://github.com/llvm/llvm-project/commit/cfbbcc544c39b008bce5612148797d0f63bd26c7.diff
LOG: [RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
Part of the shift lowering creates a (sub XLEN-1, ShAmt). When this
value is used we know that ShAmt is [0..XLEN-1]. Since XLEN is a power
of 2 we can replace the sub with an xor. This allows us to use XORI
instead of LI+SUB.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D119411
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/alu64.ll
llvm/test/CodeGen/RISCV/rotl-rotr.ll
llvm/test/CodeGen/RISCV/rv32zbs.ll
llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
llvm/test/CodeGen/RISCV/shifts.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 53bdd4b64904..1beb4dceb9d8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4112,7 +4112,7 @@ SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op,
// if Shamt-XLEN < 0: // Shamt < XLEN
// Lo = Lo << Shamt
- // Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (XLEN-1 - Shamt))
+ // Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (XLEN-1 ^ Shamt))
// else:
// Lo = 0
// Hi = Lo << (Shamt-XLEN)
@@ -4122,7 +4122,7 @@ SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op,
SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT);
SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT);
SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen);
- SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
+ SDValue XLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, XLenMinus1);
SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
@@ -4151,7 +4151,7 @@ SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
// SRA expansion:
// if Shamt-XLEN < 0: // Shamt < XLEN
- // Lo = (Lo >>u Shamt) | ((Hi << 1) << (XLEN-1 - Shamt))
+ // Lo = (Lo >>u Shamt) | ((Hi << 1) << (ShAmt ^ XLEN-1))
// Hi = Hi >>s Shamt
// else:
// Lo = Hi >>s (Shamt-XLEN);
@@ -4159,7 +4159,7 @@ SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
//
// SRL expansion:
// if Shamt-XLEN < 0: // Shamt < XLEN
- // Lo = (Lo >>u Shamt) | ((Hi << 1) << (XLEN-1 - Shamt))
+ // Lo = (Lo >>u Shamt) | ((Hi << 1) << (ShAmt ^ XLEN-1))
// Hi = Hi >>u Shamt
// else:
// Lo = Hi >>u (Shamt-XLEN);
@@ -4172,7 +4172,7 @@ SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT);
SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT);
SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen);
- SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
+ SDValue XLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, XLenMinus1);
SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
diff --git a/llvm/test/CodeGen/RISCV/alu64.ll b/llvm/test/CodeGen/RISCV/alu64.ll
index a64ad80a3ab0..2cc348c00a43 100644
--- a/llvm/test/CodeGen/RISCV/alu64.ll
+++ b/llvm/test/CodeGen/RISCV/alu64.ll
@@ -219,8 +219,7 @@ define i64 @sll(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: sll a1, a1, a2
-; RV32I-NEXT: li a3, 31
-; RV32I-NEXT: sub a3, a3, a2
+; RV32I-NEXT: xori a3, a2, 31
; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: srl a3, a4, a3
; RV32I-NEXT: or a1, a1, a3
@@ -305,8 +304,7 @@ define i64 @srl(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB15_2:
; RV32I-NEXT: srl a0, a0, a2
-; RV32I-NEXT: li a3, 31
-; RV32I-NEXT: sub a3, a3, a2
+; RV32I-NEXT: xori a3, a2, 31
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: or a0, a0, a3
@@ -332,8 +330,7 @@ define i64 @sra(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB16_2:
; RV32I-NEXT: srl a0, a0, a2
-; RV32I-NEXT: li a3, 31
-; RV32I-NEXT: sub a3, a3, a2
+; RV32I-NEXT: xori a3, a2, 31
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: or a0, a0, a3
diff --git a/llvm/test/CodeGen/RISCV/rotl-rotr.ll b/llvm/test/CodeGen/RISCV/rotl-rotr.ll
index aace4ac34216..6e8bf0dadeaf 100644
--- a/llvm/test/CodeGen/RISCV/rotl-rotr.ll
+++ b/llvm/test/CodeGen/RISCV/rotl-rotr.ll
@@ -83,45 +83,44 @@ define i32 @rotr_32(i32 %x, i32 %y) nounwind {
define i64 @rotl_64(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: rotl_64:
; RV32I: # %bb.0:
-; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: addi a5, a2, -32
-; RV32I-NEXT: li a6, 31
+; RV32I-NEXT: mv a4, a1
; RV32I-NEXT: bltz a5, .LBB2_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sll a1, a0, a5
; RV32I-NEXT: j .LBB2_3
; RV32I-NEXT: .LBB2_2:
-; RV32I-NEXT: sll a1, a3, a2
-; RV32I-NEXT: sub a4, a6, a2
-; RV32I-NEXT: srli a7, a0, 1
-; RV32I-NEXT: srl a4, a7, a4
-; RV32I-NEXT: or a1, a1, a4
+; RV32I-NEXT: sll a1, a4, a2
+; RV32I-NEXT: xori a3, a2, 31
+; RV32I-NEXT: srli a6, a0, 1
+; RV32I-NEXT: srl a3, a6, a3
+; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: .LBB2_3:
-; RV32I-NEXT: neg a7, a2
-; RV32I-NEXT: li a4, 32
-; RV32I-NEXT: sub t0, a4, a2
-; RV32I-NEXT: srl a4, a3, a7
-; RV32I-NEXT: bltz t0, .LBB2_6
+; RV32I-NEXT: neg a6, a2
+; RV32I-NEXT: li a3, 32
+; RV32I-NEXT: sub a7, a3, a2
+; RV32I-NEXT: srl a3, a4, a6
+; RV32I-NEXT: bltz a7, .LBB2_6
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: bltz a5, .LBB2_7
; RV32I-NEXT: .LBB2_5:
-; RV32I-NEXT: mv a0, a4
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB2_6:
-; RV32I-NEXT: srl a7, a0, a7
-; RV32I-NEXT: li t0, 64
-; RV32I-NEXT: sub t0, t0, a2
-; RV32I-NEXT: sub a6, a6, t0
-; RV32I-NEXT: slli a3, a3, 1
-; RV32I-NEXT: sll a3, a3, a6
-; RV32I-NEXT: or a3, a7, a3
-; RV32I-NEXT: or a1, a1, a4
-; RV32I-NEXT: mv a4, a3
+; RV32I-NEXT: srl a6, a0, a6
+; RV32I-NEXT: li a7, 64
+; RV32I-NEXT: sub a7, a7, a2
+; RV32I-NEXT: xori a7, a7, 31
+; RV32I-NEXT: slli a4, a4, 1
+; RV32I-NEXT: sll a4, a4, a7
+; RV32I-NEXT: or a4, a6, a4
+; RV32I-NEXT: or a1, a1, a3
+; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: bgez a5, .LBB2_5
; RV32I-NEXT: .LBB2_7:
; RV32I-NEXT: sll a0, a0, a2
-; RV32I-NEXT: or a4, a4, a0
-; RV32I-NEXT: mv a0, a4
+; RV32I-NEXT: or a3, a3, a0
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: ret
;
; RV64I-LABEL: rotl_64:
@@ -134,45 +133,44 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind {
;
; RV32ZBB-LABEL: rotl_64:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: mv a3, a1
; RV32ZBB-NEXT: addi a5, a2, -32
-; RV32ZBB-NEXT: li a6, 31
+; RV32ZBB-NEXT: mv a4, a1
; RV32ZBB-NEXT: bltz a5, .LBB2_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: sll a1, a0, a5
; RV32ZBB-NEXT: j .LBB2_3
; RV32ZBB-NEXT: .LBB2_2:
-; RV32ZBB-NEXT: sll a1, a3, a2
-; RV32ZBB-NEXT: sub a4, a6, a2
-; RV32ZBB-NEXT: srli a7, a0, 1
-; RV32ZBB-NEXT: srl a4, a7, a4
-; RV32ZBB-NEXT: or a1, a1, a4
+; RV32ZBB-NEXT: sll a1, a4, a2
+; RV32ZBB-NEXT: xori a3, a2, 31
+; RV32ZBB-NEXT: srli a6, a0, 1
+; RV32ZBB-NEXT: srl a3, a6, a3
+; RV32ZBB-NEXT: or a1, a1, a3
; RV32ZBB-NEXT: .LBB2_3:
-; RV32ZBB-NEXT: neg a7, a2
-; RV32ZBB-NEXT: li a4, 32
-; RV32ZBB-NEXT: sub t0, a4, a2
-; RV32ZBB-NEXT: srl a4, a3, a7
-; RV32ZBB-NEXT: bltz t0, .LBB2_6
+; RV32ZBB-NEXT: neg a6, a2
+; RV32ZBB-NEXT: li a3, 32
+; RV32ZBB-NEXT: sub a7, a3, a2
+; RV32ZBB-NEXT: srl a3, a4, a6
+; RV32ZBB-NEXT: bltz a7, .LBB2_6
; RV32ZBB-NEXT: # %bb.4:
; RV32ZBB-NEXT: bltz a5, .LBB2_7
; RV32ZBB-NEXT: .LBB2_5:
-; RV32ZBB-NEXT: mv a0, a4
+; RV32ZBB-NEXT: mv a0, a3
; RV32ZBB-NEXT: ret
; RV32ZBB-NEXT: .LBB2_6:
-; RV32ZBB-NEXT: srl a7, a0, a7
-; RV32ZBB-NEXT: li t0, 64
-; RV32ZBB-NEXT: sub t0, t0, a2
-; RV32ZBB-NEXT: sub a6, a6, t0
-; RV32ZBB-NEXT: slli a3, a3, 1
-; RV32ZBB-NEXT: sll a3, a3, a6
-; RV32ZBB-NEXT: or a3, a7, a3
-; RV32ZBB-NEXT: or a1, a1, a4
-; RV32ZBB-NEXT: mv a4, a3
+; RV32ZBB-NEXT: srl a6, a0, a6
+; RV32ZBB-NEXT: li a7, 64
+; RV32ZBB-NEXT: sub a7, a7, a2
+; RV32ZBB-NEXT: xori a7, a7, 31
+; RV32ZBB-NEXT: slli a4, a4, 1
+; RV32ZBB-NEXT: sll a4, a4, a7
+; RV32ZBB-NEXT: or a4, a6, a4
+; RV32ZBB-NEXT: or a1, a1, a3
+; RV32ZBB-NEXT: mv a3, a4
; RV32ZBB-NEXT: bgez a5, .LBB2_5
; RV32ZBB-NEXT: .LBB2_7:
; RV32ZBB-NEXT: sll a0, a0, a2
-; RV32ZBB-NEXT: or a4, a4, a0
-; RV32ZBB-NEXT: mv a0, a4
+; RV32ZBB-NEXT: or a3, a3, a0
+; RV32ZBB-NEXT: mv a0, a3
; RV32ZBB-NEXT: ret
;
; RV64ZBB-LABEL: rotl_64:
@@ -189,38 +187,37 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind {
define i64 @rotr_64(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: rotr_64:
; RV32I: # %bb.0:
-; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: addi a5, a2, -32
-; RV32I-NEXT: li a6, 31
+; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: bltz a5, .LBB3_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srl a0, a1, a5
; RV32I-NEXT: j .LBB3_3
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: srl a0, a4, a2
-; RV32I-NEXT: sub a3, a6, a2
-; RV32I-NEXT: slli a7, a1, 1
-; RV32I-NEXT: sll a3, a7, a3
+; RV32I-NEXT: xori a3, a2, 31
+; RV32I-NEXT: slli a6, a1, 1
+; RV32I-NEXT: sll a3, a6, a3
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: .LBB3_3:
-; RV32I-NEXT: neg a7, a2
+; RV32I-NEXT: neg a6, a2
; RV32I-NEXT: li a3, 32
-; RV32I-NEXT: sub t0, a3, a2
-; RV32I-NEXT: sll a3, a4, a7
-; RV32I-NEXT: bltz t0, .LBB3_6
+; RV32I-NEXT: sub a7, a3, a2
+; RV32I-NEXT: sll a3, a4, a6
+; RV32I-NEXT: bltz a7, .LBB3_6
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: bltz a5, .LBB3_7
; RV32I-NEXT: .LBB3_5:
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB3_6:
-; RV32I-NEXT: sll a7, a1, a7
-; RV32I-NEXT: li t0, 64
-; RV32I-NEXT: sub t0, t0, a2
-; RV32I-NEXT: sub a6, a6, t0
+; RV32I-NEXT: sll a6, a1, a6
+; RV32I-NEXT: li a7, 64
+; RV32I-NEXT: sub a7, a7, a2
+; RV32I-NEXT: xori a7, a7, 31
; RV32I-NEXT: srli a4, a4, 1
-; RV32I-NEXT: srl a4, a4, a6
-; RV32I-NEXT: or a4, a7, a4
+; RV32I-NEXT: srl a4, a4, a7
+; RV32I-NEXT: or a4, a6, a4
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: bgez a5, .LBB3_5
@@ -240,38 +237,37 @@ define i64 @rotr_64(i64 %x, i64 %y) nounwind {
;
; RV32ZBB-LABEL: rotr_64:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: mv a4, a0
; RV32ZBB-NEXT: addi a5, a2, -32
-; RV32ZBB-NEXT: li a6, 31
+; RV32ZBB-NEXT: mv a4, a0
; RV32ZBB-NEXT: bltz a5, .LBB3_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: srl a0, a1, a5
; RV32ZBB-NEXT: j .LBB3_3
; RV32ZBB-NEXT: .LBB3_2:
; RV32ZBB-NEXT: srl a0, a4, a2
-; RV32ZBB-NEXT: sub a3, a6, a2
-; RV32ZBB-NEXT: slli a7, a1, 1
-; RV32ZBB-NEXT: sll a3, a7, a3
+; RV32ZBB-NEXT: xori a3, a2, 31
+; RV32ZBB-NEXT: slli a6, a1, 1
+; RV32ZBB-NEXT: sll a3, a6, a3
; RV32ZBB-NEXT: or a0, a0, a3
; RV32ZBB-NEXT: .LBB3_3:
-; RV32ZBB-NEXT: neg a7, a2
+; RV32ZBB-NEXT: neg a6, a2
; RV32ZBB-NEXT: li a3, 32
-; RV32ZBB-NEXT: sub t0, a3, a2
-; RV32ZBB-NEXT: sll a3, a4, a7
-; RV32ZBB-NEXT: bltz t0, .LBB3_6
+; RV32ZBB-NEXT: sub a7, a3, a2
+; RV32ZBB-NEXT: sll a3, a4, a6
+; RV32ZBB-NEXT: bltz a7, .LBB3_6
; RV32ZBB-NEXT: # %bb.4:
; RV32ZBB-NEXT: bltz a5, .LBB3_7
; RV32ZBB-NEXT: .LBB3_5:
; RV32ZBB-NEXT: mv a1, a3
; RV32ZBB-NEXT: ret
; RV32ZBB-NEXT: .LBB3_6:
-; RV32ZBB-NEXT: sll a7, a1, a7
-; RV32ZBB-NEXT: li t0, 64
-; RV32ZBB-NEXT: sub t0, t0, a2
-; RV32ZBB-NEXT: sub a6, a6, t0
+; RV32ZBB-NEXT: sll a6, a1, a6
+; RV32ZBB-NEXT: li a7, 64
+; RV32ZBB-NEXT: sub a7, a7, a2
+; RV32ZBB-NEXT: xori a7, a7, 31
; RV32ZBB-NEXT: srli a4, a4, 1
-; RV32ZBB-NEXT: srl a4, a4, a6
-; RV32ZBB-NEXT: or a4, a7, a4
+; RV32ZBB-NEXT: srl a4, a4, a7
+; RV32ZBB-NEXT: or a4, a6, a4
; RV32ZBB-NEXT: or a0, a0, a3
; RV32ZBB-NEXT: mv a3, a4
; RV32ZBB-NEXT: bgez a5, .LBB3_5
@@ -363,34 +359,33 @@ define i32 @rotr_32_mask(i32 %x, i32 %y) nounwind {
define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: rotl_64_mask:
; RV32I: # %bb.0:
-; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: addi a5, a2, -32
-; RV32I-NEXT: li a4, 31
+; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: bltz a5, .LBB6_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sll a1, a0, a5
; RV32I-NEXT: j .LBB6_3
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: sll a1, a3, a2
-; RV32I-NEXT: sub a6, a4, a2
-; RV32I-NEXT: srli a7, a0, 1
-; RV32I-NEXT: srl a6, a7, a6
-; RV32I-NEXT: or a1, a1, a6
+; RV32I-NEXT: xori a4, a2, 31
+; RV32I-NEXT: srli a6, a0, 1
+; RV32I-NEXT: srl a4, a6, a4
+; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: .LBB6_3:
; RV32I-NEXT: neg a6, a2
-; RV32I-NEXT: andi a7, a6, 63
-; RV32I-NEXT: addi t0, a7, -32
-; RV32I-NEXT: bltz t0, .LBB6_5
+; RV32I-NEXT: andi a4, a6, 63
+; RV32I-NEXT: addi a7, a4, -32
+; RV32I-NEXT: bltz a7, .LBB6_5
; RV32I-NEXT: # %bb.4:
-; RV32I-NEXT: srl a4, a3, t0
+; RV32I-NEXT: srl a4, a3, a7
; RV32I-NEXT: bltz a5, .LBB6_6
; RV32I-NEXT: j .LBB6_7
; RV32I-NEXT: .LBB6_5:
-; RV32I-NEXT: srl t0, a0, a6
-; RV32I-NEXT: sub a4, a4, a7
-; RV32I-NEXT: slli a7, a3, 1
-; RV32I-NEXT: sll a4, a7, a4
-; RV32I-NEXT: or a4, t0, a4
+; RV32I-NEXT: srl a7, a0, a6
+; RV32I-NEXT: xori a4, a4, 31
+; RV32I-NEXT: slli t0, a3, 1
+; RV32I-NEXT: sll a4, t0, a4
+; RV32I-NEXT: or a4, a7, a4
; RV32I-NEXT: srl a3, a3, a6
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: bgez a5, .LBB6_7
@@ -411,34 +406,33 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
;
; RV32ZBB-LABEL: rotl_64_mask:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: mv a3, a1
; RV32ZBB-NEXT: addi a5, a2, -32
-; RV32ZBB-NEXT: li a4, 31
+; RV32ZBB-NEXT: mv a3, a1
; RV32ZBB-NEXT: bltz a5, .LBB6_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: sll a1, a0, a5
; RV32ZBB-NEXT: j .LBB6_3
; RV32ZBB-NEXT: .LBB6_2:
; RV32ZBB-NEXT: sll a1, a3, a2
-; RV32ZBB-NEXT: sub a6, a4, a2
-; RV32ZBB-NEXT: srli a7, a0, 1
-; RV32ZBB-NEXT: srl a6, a7, a6
-; RV32ZBB-NEXT: or a1, a1, a6
+; RV32ZBB-NEXT: xori a4, a2, 31
+; RV32ZBB-NEXT: srli a6, a0, 1
+; RV32ZBB-NEXT: srl a4, a6, a4
+; RV32ZBB-NEXT: or a1, a1, a4
; RV32ZBB-NEXT: .LBB6_3:
; RV32ZBB-NEXT: neg a6, a2
-; RV32ZBB-NEXT: andi a7, a6, 63
-; RV32ZBB-NEXT: addi t0, a7, -32
-; RV32ZBB-NEXT: bltz t0, .LBB6_5
+; RV32ZBB-NEXT: andi a4, a6, 63
+; RV32ZBB-NEXT: addi a7, a4, -32
+; RV32ZBB-NEXT: bltz a7, .LBB6_5
; RV32ZBB-NEXT: # %bb.4:
-; RV32ZBB-NEXT: srl a4, a3, t0
+; RV32ZBB-NEXT: srl a4, a3, a7
; RV32ZBB-NEXT: bltz a5, .LBB6_6
; RV32ZBB-NEXT: j .LBB6_7
; RV32ZBB-NEXT: .LBB6_5:
-; RV32ZBB-NEXT: srl t0, a0, a6
-; RV32ZBB-NEXT: sub a4, a4, a7
-; RV32ZBB-NEXT: slli a7, a3, 1
-; RV32ZBB-NEXT: sll a4, a7, a4
-; RV32ZBB-NEXT: or a4, t0, a4
+; RV32ZBB-NEXT: srl a7, a0, a6
+; RV32ZBB-NEXT: xori a4, a4, 31
+; RV32ZBB-NEXT: slli t0, a3, 1
+; RV32ZBB-NEXT: sll a4, t0, a4
+; RV32ZBB-NEXT: or a4, a7, a4
; RV32ZBB-NEXT: srl a3, a3, a6
; RV32ZBB-NEXT: or a1, a1, a3
; RV32ZBB-NEXT: bgez a5, .LBB6_7
@@ -464,34 +458,33 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: rotr_64_mask:
; RV32I: # %bb.0:
-; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: addi a5, a2, -32
-; RV32I-NEXT: li a4, 31
+; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: bltz a5, .LBB7_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srl a0, a1, a5
; RV32I-NEXT: j .LBB7_3
; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: srl a0, a3, a2
-; RV32I-NEXT: sub a6, a4, a2
-; RV32I-NEXT: slli a7, a1, 1
-; RV32I-NEXT: sll a6, a7, a6
-; RV32I-NEXT: or a0, a0, a6
+; RV32I-NEXT: xori a4, a2, 31
+; RV32I-NEXT: slli a6, a1, 1
+; RV32I-NEXT: sll a4, a6, a4
+; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: neg a6, a2
-; RV32I-NEXT: andi a7, a6, 63
-; RV32I-NEXT: addi t0, a7, -32
-; RV32I-NEXT: bltz t0, .LBB7_5
+; RV32I-NEXT: andi a4, a6, 63
+; RV32I-NEXT: addi a7, a4, -32
+; RV32I-NEXT: bltz a7, .LBB7_5
; RV32I-NEXT: # %bb.4:
-; RV32I-NEXT: sll a4, a3, t0
+; RV32I-NEXT: sll a4, a3, a7
; RV32I-NEXT: bltz a5, .LBB7_6
; RV32I-NEXT: j .LBB7_7
; RV32I-NEXT: .LBB7_5:
-; RV32I-NEXT: sll t0, a1, a6
-; RV32I-NEXT: sub a4, a4, a7
-; RV32I-NEXT: srli a7, a3, 1
-; RV32I-NEXT: srl a4, a7, a4
-; RV32I-NEXT: or a4, t0, a4
+; RV32I-NEXT: sll a7, a1, a6
+; RV32I-NEXT: xori a4, a4, 31
+; RV32I-NEXT: srli t0, a3, 1
+; RV32I-NEXT: srl a4, t0, a4
+; RV32I-NEXT: or a4, a7, a4
; RV32I-NEXT: sll a3, a3, a6
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: bgez a5, .LBB7_7
@@ -512,34 +505,33 @@ define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind {
;
; RV32ZBB-LABEL: rotr_64_mask:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: mv a3, a0
; RV32ZBB-NEXT: addi a5, a2, -32
-; RV32ZBB-NEXT: li a4, 31
+; RV32ZBB-NEXT: mv a3, a0
; RV32ZBB-NEXT: bltz a5, .LBB7_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: srl a0, a1, a5
; RV32ZBB-NEXT: j .LBB7_3
; RV32ZBB-NEXT: .LBB7_2:
; RV32ZBB-NEXT: srl a0, a3, a2
-; RV32ZBB-NEXT: sub a6, a4, a2
-; RV32ZBB-NEXT: slli a7, a1, 1
-; RV32ZBB-NEXT: sll a6, a7, a6
-; RV32ZBB-NEXT: or a0, a0, a6
+; RV32ZBB-NEXT: xori a4, a2, 31
+; RV32ZBB-NEXT: slli a6, a1, 1
+; RV32ZBB-NEXT: sll a4, a6, a4
+; RV32ZBB-NEXT: or a0, a0, a4
; RV32ZBB-NEXT: .LBB7_3:
; RV32ZBB-NEXT: neg a6, a2
-; RV32ZBB-NEXT: andi a7, a6, 63
-; RV32ZBB-NEXT: addi t0, a7, -32
-; RV32ZBB-NEXT: bltz t0, .LBB7_5
+; RV32ZBB-NEXT: andi a4, a6, 63
+; RV32ZBB-NEXT: addi a7, a4, -32
+; RV32ZBB-NEXT: bltz a7, .LBB7_5
; RV32ZBB-NEXT: # %bb.4:
-; RV32ZBB-NEXT: sll a4, a3, t0
+; RV32ZBB-NEXT: sll a4, a3, a7
; RV32ZBB-NEXT: bltz a5, .LBB7_6
; RV32ZBB-NEXT: j .LBB7_7
; RV32ZBB-NEXT: .LBB7_5:
-; RV32ZBB-NEXT: sll t0, a1, a6
-; RV32ZBB-NEXT: sub a4, a4, a7
-; RV32ZBB-NEXT: srli a7, a3, 1
-; RV32ZBB-NEXT: srl a4, a7, a4
-; RV32ZBB-NEXT: or a4, t0, a4
+; RV32ZBB-NEXT: sll a7, a1, a6
+; RV32ZBB-NEXT: xori a4, a4, 31
+; RV32ZBB-NEXT: srli t0, a3, 1
+; RV32ZBB-NEXT: srl a4, t0, a4
+; RV32ZBB-NEXT: or a4, a7, a4
; RV32ZBB-NEXT: sll a3, a3, a6
; RV32ZBB-NEXT: or a0, a0, a3
; RV32ZBB-NEXT: bgez a5, .LBB7_7
diff --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll
index 42fd06f94a66..ee05d1152f37 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll
@@ -288,9 +288,8 @@ define i64 @bext_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: j .LBB12_3
; RV32I-NEXT: .LBB12_2:
; RV32I-NEXT: srl a0, a0, a2
-; RV32I-NEXT: li a2, 31
-; RV32I-NEXT: sub a2, a2, a3
; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: xori a2, a3, 31
; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: .LBB12_3:
@@ -308,9 +307,8 @@ define i64 @bext_i64(i64 %a, i64 %b) nounwind {
; RV32ZBS-NEXT: j .LBB12_3
; RV32ZBS-NEXT: .LBB12_2:
; RV32ZBS-NEXT: srl a0, a0, a2
-; RV32ZBS-NEXT: li a2, 31
-; RV32ZBS-NEXT: sub a2, a2, a3
; RV32ZBS-NEXT: slli a1, a1, 1
+; RV32ZBS-NEXT: xori a2, a3, 31
; RV32ZBS-NEXT: sll a1, a1, a2
; RV32ZBS-NEXT: or a0, a0, a1
; RV32ZBS-NEXT: .LBB12_3:
diff --git a/llvm/test/CodeGen/RISCV/shift-masked-shamt.ll b/llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
index cb57757d815b..760955abf7e4 100644
--- a/llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
+++ b/llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
@@ -170,9 +170,8 @@ define i64 @sll_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB9_2:
; RV32I-NEXT: sll a1, a1, a2
-; RV32I-NEXT: li a4, 31
-; RV32I-NEXT: sub a3, a4, a3
; RV32I-NEXT: srli a4, a0, 1
+; RV32I-NEXT: xori a3, a3, 31
; RV32I-NEXT: srl a3, a4, a3
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: sll a0, a0, a2
@@ -202,9 +201,8 @@ define i64 @srl_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB10_2:
; RV32I-NEXT: srl a0, a0, a2
-; RV32I-NEXT: li a4, 31
-; RV32I-NEXT: sub a3, a4, a3
; RV32I-NEXT: slli a4, a1, 1
+; RV32I-NEXT: xori a3, a3, 31
; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: srl a1, a1, a2
@@ -234,9 +232,8 @@ define i64 @sra_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: srl a0, a0, a2
-; RV32I-NEXT: li a4, 31
-; RV32I-NEXT: sub a3, a4, a3
; RV32I-NEXT: slli a4, a1, 1
+; RV32I-NEXT: xori a3, a3, 31
; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: sra a1, a1, a2
diff --git a/llvm/test/CodeGen/RISCV/shifts.ll b/llvm/test/CodeGen/RISCV/shifts.ll
index 7e63aa91262a..3d5e8529ef35 100644
--- a/llvm/test/CodeGen/RISCV/shifts.ll
+++ b/llvm/test/CodeGen/RISCV/shifts.ll
@@ -21,8 +21,7 @@ define i64 @lshr64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: srl a0, a0, a2
-; RV32I-NEXT: li a3, 31
-; RV32I-NEXT: sub a3, a3, a2
+; RV32I-NEXT: xori a3, a2, 31
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: or a0, a0, a3
@@ -66,8 +65,7 @@ define i64 @ashr64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT: srl a0, a0, a2
-; RV32I-NEXT: li a3, 31
-; RV32I-NEXT: sub a3, a3, a2
+; RV32I-NEXT: xori a3, a2, 31
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: or a0, a0, a3
@@ -111,8 +109,7 @@ define i64 @shl64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: sll a1, a1, a2
-; RV32I-NEXT: li a3, 31
-; RV32I-NEXT: sub a3, a3, a2
+; RV32I-NEXT: xori a3, a2, 31
; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: srl a3, a4, a3
; RV32I-NEXT: or a1, a1, a3
@@ -153,28 +150,27 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: neg a6, a2
; RV32I-NEXT: li a3, 64
-; RV32I-NEXT: li t2, 31
; RV32I-NEXT: li a7, 32
; RV32I-NEXT: sub t1, a7, a2
; RV32I-NEXT: sll t0, a5, a6
; RV32I-NEXT: bltz t1, .LBB6_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: mv t6, t0
+; RV32I-NEXT: mv t2, t0
; RV32I-NEXT: j .LBB6_3
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: sll a6, a4, a6
; RV32I-NEXT: sub a7, a3, a2
-; RV32I-NEXT: sub a7, t2, a7
-; RV32I-NEXT: srli t3, a5, 1
-; RV32I-NEXT: srl a7, t3, a7
-; RV32I-NEXT: or t6, a6, a7
+; RV32I-NEXT: xori a7, a7, 31
+; RV32I-NEXT: srli t2, a5, 1
+; RV32I-NEXT: srl a7, t2, a7
+; RV32I-NEXT: or t2, a6, a7
; RV32I-NEXT: .LBB6_3:
; RV32I-NEXT: lw t5, 4(a1)
; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: bgez a6, .LBB6_5
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: srl a7, t5, a2
-; RV32I-NEXT: or t6, t6, a7
+; RV32I-NEXT: or t2, t2, a7
; RV32I-NEXT: .LBB6_5:
; RV32I-NEXT: addi t4, a2, -96
; RV32I-NEXT: addi t3, a2, -64
@@ -187,15 +183,15 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: srl a7, a4, t3
; RV32I-NEXT: bltu a2, a3, .LBB6_9
; RV32I-NEXT: .LBB6_8:
-; RV32I-NEXT: mv t6, a7
+; RV32I-NEXT: mv t2, a7
; RV32I-NEXT: .LBB6_9:
; RV32I-NEXT: mv a7, t5
; RV32I-NEXT: beqz a2, .LBB6_11
; RV32I-NEXT: # %bb.10:
-; RV32I-NEXT: mv a7, t6
+; RV32I-NEXT: mv a7, t2
; RV32I-NEXT: .LBB6_11:
; RV32I-NEXT: lw a1, 0(a1)
-; RV32I-NEXT: sub t2, t2, a2
+; RV32I-NEXT: xori t2, a2, 31
; RV32I-NEXT: bltz a6, .LBB6_13
; RV32I-NEXT: # %bb.12:
; RV32I-NEXT: srl t5, t5, a6
@@ -217,11 +213,10 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: bgeu a2, a3, .LBB6_18
; RV32I-NEXT: j .LBB6_19
; RV32I-NEXT: .LBB6_17:
-; RV32I-NEXT: li t1, 95
-; RV32I-NEXT: sub t1, t1, a2
-; RV32I-NEXT: sll t1, t0, t1
-; RV32I-NEXT: srl t3, a5, t3
-; RV32I-NEXT: or t1, t3, t1
+; RV32I-NEXT: srl t1, a5, t3
+; RV32I-NEXT: xori t3, t3, 31
+; RV32I-NEXT: sll t3, t0, t3
+; RV32I-NEXT: or t1, t1, t3
; RV32I-NEXT: bltu a2, a3, .LBB6_19
; RV32I-NEXT: .LBB6_18:
; RV32I-NEXT: mv t5, t1
@@ -271,8 +266,7 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: srl a0, a0, a2
-; RV64I-NEXT: li a3, 63
-; RV64I-NEXT: sub a3, a3, a2
+; RV64I-NEXT: xori a3, a2, 63
; RV64I-NEXT: slli a4, a1, 1
; RV64I-NEXT: sll a3, a4, a3
; RV64I-NEXT: or a0, a0, a3
@@ -292,30 +286,29 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: neg a6, a2
; RV32I-NEXT: li a3, 64
-; RV32I-NEXT: li t3, 31
; RV32I-NEXT: li a7, 32
; RV32I-NEXT: sub t2, a7, a2
; RV32I-NEXT: sll t1, a5, a6
; RV32I-NEXT: bltz t2, .LBB7_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: mv s0, t1
+; RV32I-NEXT: mv t4, t1
; RV32I-NEXT: j .LBB7_3
; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: sll a6, a4, a6
; RV32I-NEXT: sub a7, a3, a2
-; RV32I-NEXT: sub a7, t3, a7
+; RV32I-NEXT: xori a7, a7, 31
; RV32I-NEXT: srli t0, a5, 1
; RV32I-NEXT: srl a7, t0, a7
-; RV32I-NEXT: or s0, a6, a7
+; RV32I-NEXT: or t4, a6, a7
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: lw t6, 4(a1)
; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: bgez a6, .LBB7_5
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: srl a7, t6, a2
-; RV32I-NEXT: or s0, s0, a7
+; RV32I-NEXT: or t4, t4, a7
; RV32I-NEXT: .LBB7_5:
-; RV32I-NEXT: addi t4, a2, -64
+; RV32I-NEXT: addi t3, a2, -64
; RV32I-NEXT: addi t5, a2, -96
; RV32I-NEXT: srai a7, a4, 31
; RV32I-NEXT: bltz t5, .LBB7_7
@@ -324,18 +317,18 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: bgeu a2, a3, .LBB7_8
; RV32I-NEXT: j .LBB7_9
; RV32I-NEXT: .LBB7_7:
-; RV32I-NEXT: sra t0, a4, t4
+; RV32I-NEXT: sra t0, a4, t3
; RV32I-NEXT: bltu a2, a3, .LBB7_9
; RV32I-NEXT: .LBB7_8:
-; RV32I-NEXT: mv s0, t0
+; RV32I-NEXT: mv t4, t0
; RV32I-NEXT: .LBB7_9:
; RV32I-NEXT: mv t0, t6
; RV32I-NEXT: beqz a2, .LBB7_11
; RV32I-NEXT: # %bb.10:
-; RV32I-NEXT: mv t0, s0
+; RV32I-NEXT: mv t0, t4
; RV32I-NEXT: .LBB7_11:
; RV32I-NEXT: lw a1, 0(a1)
-; RV32I-NEXT: sub t3, t3, a2
+; RV32I-NEXT: xori t4, a2, 31
; RV32I-NEXT: bltz a6, .LBB7_13
; RV32I-NEXT: # %bb.12:
; RV32I-NEXT: srl t6, t6, a6
@@ -344,7 +337,7 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: .LBB7_13:
; RV32I-NEXT: srl s0, a1, a2
; RV32I-NEXT: slli t6, t6, 1
-; RV32I-NEXT: sll t6, t6, t3
+; RV32I-NEXT: sll t6, t6, t4
; RV32I-NEXT: or t6, s0, t6
; RV32I-NEXT: bgez t2, .LBB7_15
; RV32I-NEXT: .LBB7_14:
@@ -357,11 +350,10 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: bgeu a2, a3, .LBB7_18
; RV32I-NEXT: j .LBB7_19
; RV32I-NEXT: .LBB7_17:
-; RV32I-NEXT: li t2, 95
-; RV32I-NEXT: sub t2, t2, a2
-; RV32I-NEXT: sll t2, t1, t2
-; RV32I-NEXT: srl t4, a5, t4
-; RV32I-NEXT: or t2, t4, t2
+; RV32I-NEXT: srl t2, a5, t3
+; RV32I-NEXT: xori t3, t3, 31
+; RV32I-NEXT: sll t3, t1, t3
+; RV32I-NEXT: or t2, t2, t3
; RV32I-NEXT: bltu a2, a3, .LBB7_19
; RV32I-NEXT: .LBB7_18:
; RV32I-NEXT: mv t6, t2
@@ -378,7 +370,7 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: bgez a6, .LBB7_21
; RV32I-NEXT: .LBB7_23:
; RV32I-NEXT: srl a5, a5, a2
-; RV32I-NEXT: sll t1, t1, t3
+; RV32I-NEXT: sll t1, t1, t4
; RV32I-NEXT: or a5, a5, t1
; RV32I-NEXT: bltu a2, a3, .LBB7_25
; RV32I-NEXT: .LBB7_24:
@@ -413,8 +405,7 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB7_2:
; RV64I-NEXT: srl a0, a0, a2
-; RV64I-NEXT: li a3, 63
-; RV64I-NEXT: sub a3, a3, a2
+; RV64I-NEXT: xori a3, a2, 63
; RV64I-NEXT: slli a4, a1, 1
; RV64I-NEXT: sll a3, a4, a3
; RV64I-NEXT: or a0, a0, a3
@@ -432,28 +423,27 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: lw a4, 0(a1)
; RV32I-NEXT: neg a6, a2
; RV32I-NEXT: li a3, 64
-; RV32I-NEXT: li t2, 31
; RV32I-NEXT: li a7, 32
; RV32I-NEXT: sub t1, a7, a2
; RV32I-NEXT: srl t0, a5, a6
; RV32I-NEXT: bltz t1, .LBB8_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: mv t6, t0
+; RV32I-NEXT: mv t2, t0
; RV32I-NEXT: j .LBB8_3
; RV32I-NEXT: .LBB8_2:
; RV32I-NEXT: srl a6, a4, a6
; RV32I-NEXT: sub a7, a3, a2
-; RV32I-NEXT: sub a7, t2, a7
-; RV32I-NEXT: slli t3, a5, 1
-; RV32I-NEXT: sll a7, t3, a7
-; RV32I-NEXT: or t6, a6, a7
+; RV32I-NEXT: xori a7, a7, 31
+; RV32I-NEXT: slli t2, a5, 1
+; RV32I-NEXT: sll a7, t2, a7
+; RV32I-NEXT: or t2, a6, a7
; RV32I-NEXT: .LBB8_3:
; RV32I-NEXT: lw t5, 8(a1)
; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: bgez a6, .LBB8_5
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: sll a7, t5, a2
-; RV32I-NEXT: or t6, t6, a7
+; RV32I-NEXT: or t2, t2, a7
; RV32I-NEXT: .LBB8_5:
; RV32I-NEXT: addi t4, a2, -96
; RV32I-NEXT: addi t3, a2, -64
@@ -466,15 +456,15 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sll a7, a4, t3
; RV32I-NEXT: bltu a2, a3, .LBB8_9
; RV32I-NEXT: .LBB8_8:
-; RV32I-NEXT: mv t6, a7
+; RV32I-NEXT: mv t2, a7
; RV32I-NEXT: .LBB8_9:
; RV32I-NEXT: mv a7, t5
; RV32I-NEXT: beqz a2, .LBB8_11
; RV32I-NEXT: # %bb.10:
-; RV32I-NEXT: mv a7, t6
+; RV32I-NEXT: mv a7, t2
; RV32I-NEXT: .LBB8_11:
; RV32I-NEXT: lw a1, 12(a1)
-; RV32I-NEXT: sub t2, t2, a2
+; RV32I-NEXT: xori t2, a2, 31
; RV32I-NEXT: bltz a6, .LBB8_13
; RV32I-NEXT: # %bb.12:
; RV32I-NEXT: sll t5, t5, a6
@@ -496,11 +486,10 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: bgeu a2, a3, .LBB8_18
; RV32I-NEXT: j .LBB8_19
; RV32I-NEXT: .LBB8_17:
-; RV32I-NEXT: li t1, 95
-; RV32I-NEXT: sub t1, t1, a2
-; RV32I-NEXT: srl t1, t0, t1
-; RV32I-NEXT: sll t3, a5, t3
-; RV32I-NEXT: or t1, t3, t1
+; RV32I-NEXT: sll t1, a5, t3
+; RV32I-NEXT: xori t3, t3, 31
+; RV32I-NEXT: srl t3, t0, t3
+; RV32I-NEXT: or t1, t1, t3
; RV32I-NEXT: bltu a2, a3, .LBB8_19
; RV32I-NEXT: .LBB8_18:
; RV32I-NEXT: mv t5, t1
@@ -550,8 +539,7 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB8_2:
; RV64I-NEXT: sll a1, a1, a2
-; RV64I-NEXT: li a3, 63
-; RV64I-NEXT: sub a3, a3, a2
+; RV64I-NEXT: xori a3, a2, 63
; RV64I-NEXT: srli a4, a0, 1
; RV64I-NEXT: srl a3, a4, a3
; RV64I-NEXT: or a1, a1, a3
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