[PATCH] D119939: [AMDGPU][MC][GFX10] Added an alias for HW_REG_HW_ID1
Dmitry Preobrazhensky via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 16 06:24:43 PST 2022
dp created this revision.
dp added reviewers: arsenm, rampitec.
Herald added subscribers: foad, jeroen.dobbelaere, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
dp requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.
Enabled HW_REG_HW_ID as an alias for HW_REG_HW_ID1. This is required for compatibility with existing code.
https://reviews.llvm.org/D119939
Files:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
llvm/test/MC/AMDGPU/sopk.s
Index: llvm/test/MC/AMDGPU/sopk.s
===================================================================
--- llvm/test/MC/AMDGPU/sopk.s
+++ llvm/test/MC/AMDGPU/sopk.s
@@ -230,7 +230,7 @@
s_setreg_b32 hwreg(HW_REG_HW_ID), s2
// SICI: s_setreg_b32 hwreg(HW_REG_HW_ID), s2 ; encoding: [0x04,0xf8,0x82,0xb9]
// VI9: s_setreg_b32 hwreg(HW_REG_HW_ID), s2 ; encoding: [0x04,0xf8,0x02,0xb9]
-// NOGFX10: error: specified hardware register is not supported on this GPU
+// GFX10: s_setreg_b32 hwreg(HW_REG_HW_ID1), s2 ; encoding: [0x17,0xf8,0x82,0xb9]
s_setreg_b32 hwreg(HW_REG_HW_ID1), s2
// NOSICIVI: error: specified hardware register is not supported on this GPU
Index: llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
===================================================================
--- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -601,7 +601,7 @@
namespace Hwreg {
LLVM_READONLY
-int64_t getHwregId(const StringRef Name);
+int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
LLVM_READNONE
bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
Index: llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1026,7 +1026,9 @@
namespace Hwreg {
-int64_t getHwregId(const StringRef Name) {
+int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI) {
+ if (isGFX10(STI) && Name == "HW_REG_HW_ID") // An alias
+ return ID_HW_ID1;
for (int Id = ID_SYMBOLIC_FIRST_; Id < ID_SYMBOLIC_LAST_; ++Id) {
if (IdSymbolic[Id] && Name == IdSymbolic[Id])
return Id;
Index: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -6176,7 +6176,7 @@
// The register may be specified by name or using a numeric code
HwReg.Loc = getLoc();
if (isToken(AsmToken::Identifier) &&
- (HwReg.Id = getHwregId(getTokenStr())) >= 0) {
+ (HwReg.Id = getHwregId(getTokenStr(), getSTI())) >= 0) {
HwReg.IsSymbolic = true;
lex(); // skip register name
} else if (!parseExpr(HwReg.Id, "a register name")) {
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