[PATCH] D118026: [RISCV] Improve the condition of hasRVVFrameObject.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:976
+      for (const auto &MO : MI.uses())
+        if (MO.isReg() && MO.getReg() == RISCV::VL)
+          return true;
----------------
craig.topper wrote:
> craig.topper wrote:
> > kito-cheng wrote:
> > > jacquesguan wrote:
> > > > craig.topper wrote:
> > > > > Is it possible to write a function that contains nothing but whole register loads/stores/moves such that no instruction access VL but needs to spill a register?
> > > > I am not sure about this, I think maybe it's not possible to generate independent whole register instructions. Do you have any good opinion about the condition?
> > > Maybe check any vector register are appear in the function either use or def?
> > This generates a single whole register load
> > 
> > ```
> > #include <riscv_vector.h>
> > 
> > vfloat32m4_t foo(vfloat32m4_t *a) {
> >   return *a;
> > }
> > ```
> That was only meant as an example of how register instrutions can be generated. Not that it creates scalable frame object.
Done, I changed the condition to check if there ia any VR or VTYPE. 


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  https://reviews.llvm.org/D118026/new/

https://reviews.llvm.org/D118026