[PATCH] D119911: AMDGPU: Always reserve VGPR for AGPR copies on gfx908

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, cdevadas, AMDGPU.
Herald added subscribers: foad, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, qcolombet, MatzeB.
arsenm requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

Just because there aren't AGPRs in the original program doesn't mean
the register allocator can't choose to use them (unless we were to
forcibly reserve all AGPRs if there weren't any uses). This happens in
high pressure situations and introduces copies to avoid spills.

      

In this test, the allocator ends up introducing a copy from SGPR to
AGPR which requires an intermediate VGPR. I don't believe it would
introduce a copy from AGPR to AGPR in this situation, since it would
be trying to use an intermediate with a different class.

      

Theoretically this is also broken on gfx90a, but I have been unable to
come up with a testcase.


https://reviews.llvm.org/D119911

Files:
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
  llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
  llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D119911.409118.patch
Type: text/x-patch
Size: 69666 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220216/75b46fbc/attachment.bin>