[PATCH] D119475: [AMDGPU] Add scheduler pass to rematerialize trivial defs

[Vang Thao via Phabricator via llvm-commits]

vangthao updated this revision to Diff 409055.
vangthao added a comment.

Combine logic for live-throughs and uses in block. Update RegionBegin for sink from and to region. Increment RegionIdx when we skip a region due to it being size 0 or 1 else next iteration will still point to this region.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119475/new/

https://reviews.llvm.org/D119475

Files:
  llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
  llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
  llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
  llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
  llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
  llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir

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