[PATCH] D119868: [SystemZ][z/OS] Fix f32 variadic argument assertion

[Mubariz Afzal via Phabricator via llvm-commits]

mubarizafzal updated this revision to Diff 408974.
mubarizafzal added a comment.

Allow f32 in bitcast case and add test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119868/new/

https://reviews.llvm.org/D119868

Files:
  llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
  llvm/test/CodeGen/SystemZ/call-zos-vararg.ll


Index: llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
===================================================================
--- llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
+++ llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
@@ -189,7 +189,30 @@
   ret i64 %retval
 }
 
+; CHECK-LABEL: call_vararg_float0
+; CHECK:       lghi  1, 1
+; CHECK:       llihf 2, 1073692672
+define i64 @call_vararg_float0() {
+entry:
+  %retval = call i64 (i64, ...) @pass_vararg2(i64 1, float 1.953125)
+  ret i64 %retval
+}
+
+; CHECK-LABEL: call_vararg_float1
+; CHECK:       llihf 0, 1073692672
+; CHECK-NEXT:  stg  0, 2200(4)
+; CHECK:       larl  1, @CPI21_0
+; CHECK-NEXT:  le  0, 0(1)
+; CHECK:       llihh 2, 16384
+; CHECK:       llihh 3, 16392
+define i64 @call_vararg_float1() {
+entry:
+  %retval = call i64 (float, ...) @pass_vararg4(float 1.0, float 2.0, float 3.0, float 1.953125)
+  ret i64 %retval
+}
+
 declare i64 @pass_vararg0(i64 %arg0, i64 %arg1, ...)
 declare i64 @pass_vararg1(fp128 %arg0, ...)
 declare i64 @pass_vararg2(i64 %arg0, ...)
 declare i64 @pass_vararg3(...)
+declare i64 @pass_vararg4(float, ...)
Index: llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
===================================================================
--- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -1360,8 +1360,13 @@
     return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
   case CCValAssign::BCvt: {
     assert(VA.getLocVT() == MVT::i64 || VA.getLocVT() == MVT::i128);
-    assert(VA.getValVT().isVector() || VA.getValVT() == MVT::f64 ||
+    assert(VA.getValVT().isVector() || VA.getValVT() == MVT::f32 ||
+           VA.getValVT() == MVT::f64 ||
            VA.getValVT() == MVT::f128);
+    // For an f32 vararg we need to first promote it to an f64 and then
+    // bitcast it to an i64.
+    if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i64)
+      Value = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f64, Value);
     MVT BitCastToType = VA.getValVT().isVector() && VA.getLocVT() == MVT::i64
                             ? MVT::v2i64
                             : VA.getLocVT();


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