[PATCH] D118299: [Spill2Reg][2/9] This patch adds spill/reload collection.
Vasileios Porpodas via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 15 10:59:43 PST 2022
vporpo marked an inline comment as done.
vporpo added inline comments.
================
Comment at: llvm/lib/CodeGen/Spill2Reg.cpp:160
+ auto &Entry = StackSlotData[StackSlot];
+ unsigned MemBits = TRI->getRegSizeInBits(MO->getReg(), *MRI);
+ if (SkipEntry(StackSlot, MemBits, MI.getOpcode())) {
----------------
arsenm wrote:
> I wouldn't assume the memory size is the same as the register size
Perhaps the variable name is bad. MemBits is the size of the register and we are using it later in the code generation phase to choose which insert/extract instruction to use.
Wdyt about renaming it to SpillBits ?
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D118299/new/
https://reviews.llvm.org/D118299
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