[PATCH] D119424: [AArch64][SVE] Invert VSelect operand order and condition for predicated arithmetic operations

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau updated this revision to Diff 408869.
MattDevereau added a comment.

Removed `SetCCOp0 == NOp2` and `SetCCOp0 != NOp1` exit conditions
Added SelectA != SelectB.getOperand(0) exit condition


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119424/new/

https://reviews.llvm.org/D119424

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fp-reciprocal.ll
  llvm/test/CodeGen/AArch64/sve-select.ll

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