[PATCH] D118026: [RISCV] Improve the condition of hasRVVFrameObject.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:976
+      for (const auto &MO : MI.uses())
+        if (MO.isReg() && MO.getReg() == RISCV::VL)
+          return true;
----------------
kito-cheng wrote:
> jacquesguan wrote:
> > craig.topper wrote:
> > > Is it possible to write a function that contains nothing but whole register loads/stores/moves such that no instruction access VL but needs to spill a register?
> > I am not sure about this, I think maybe it's not possible to generate independent whole register instructions. Do you have any good opinion about the condition?
> Maybe check any vector register are appear in the function either use or def?
This generates a single whole register load

```
#include <riscv_vector.h>

vfloat32m4_t foo(vfloat32m4_t *a) {
  return *a;
}
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118026/new/

https://reviews.llvm.org/D118026