[PATCH] D118663: [AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt.

[Micah Weston via Phabricator via llvm-commits]

red1bluelost updated this revision to Diff 408675.
red1bluelost added a comment.

Fixes cross basic block found in ClangBuiltLinux.

The issue was the physical register was being replaced which screws up coherency
across basic blocks. The scenario was added as a test case. Before, the XZR register
was replaced every where with a new virtual register screwing up the MIR.

In the case where DstReg is physical, we should reuse it rather than making a new
virtual register. This fix ensures that a physical DstReg is preversed while
a virtual DstReg is replaced with a new virtual register.

Thank you for testing and finding the errors!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118663/new/

https://reviews.llvm.org/D118663

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.h
  llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
  llvm/test/CodeGen/AArch64/addsub.ll
  llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll

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